DETAIL OF CONTROL BITS AND REGISTER MAPPING" />
參數(shù)資料
型號： MCZ33903BS5EK
廠商： Freescale Semiconductor
文件頁數(shù)： 73/106頁
文件大?。?/td> 0K
描述： IC SBC CAN HS 5.0V 32SOIC
標(biāo)準(zhǔn)包裝： 42
應(yīng)用： 系統(tǒng)基礎(chǔ)芯片
接口： CAN，LIN
電源電壓： 5.5 V ~ 28 V
封裝/外殼： 32-SSOP（0.295"，7.50mm 寬）裸露焊盤
供應(yīng)商設(shè)備封裝： 32-SOICW 裸露焊盤
包裝： 管件
安裝類型： 表面貼裝
Analog Integrated Circuit Device Data
Freescale Semiconductor
69
33903/4/5
SERIAL PERIPHERAL INTERFACE
DETAIL OF CONTROL BITS AND REGISTER MAPPING
INIT REGISTERS
Note: these registers can be written only in INIT mode
Table 17. Initialization Regulator Registers, INIT REG (note: register can be written only in INIT mode)
MOSI First Byte [15-8]
[b_15 b_14] 0_0101 [P/N]
MOSI Second Byte, bits 7-0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
01 00 _ 101 P
I/O-x sync
VDDL rst[1]
VDDL rst[0]
VDD rstD[1]
VDD rstD[0]
VAUX5/3
Cyclic on[1]
Cyclic on[0]
Default state
1
0
Condition for default
POR
Bit
Description
b7
I/O-x sync - Determine if I/O-1 is sensed during I/O-0 activation, when cyclic sense function is selected
0
I/O-1 sense anytime
1
I/O-1 sense during I/O-0 activation
b6, b5
VDDL RST[1] VDDL RST[0] - Select the VDD undervoltage threshold, to activate RST pin and/or INT
00
Reset at approx 0.9 VDD.
01
INT at approx 0.9 VDD, Reset at approx 0.7 VDD
10
Reset at approx 0.7 VDD
11
Reset at approx 0.9 VDD.
b4, b3
VDD RSTD[1] VDD RSTD[0] - Select the RST pin low lev duration, after VDD rises above the VDD undervoltage threshold
00
1.0 ms
01
5.0 ms
10
10 ms
11
20 ms
b2
[VAUX 5/3] - Select Vauxilary output voltage
0
VAUX = 3.3 V
1
VAUX = 5.0 V
b1, b0
Cyclic on[1] Cyclic on[0] - Determine I/O-0 activation time, when cyclic sense function is selected
00
200
s (typical value. Ref. to dynamic parameters for exact value)
01
400
s (typical value. Ref. to dynamic parameters for exact value)
10
800
s (typical value. Ref. to dynamic parameters for exact value)
11
1600
s (typical value. Ref. to dynamic parameters for exact value)
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