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| 型號(hào)： | MCZ33904B5EKR2 |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 77/106頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | SENSOR ABS PRESS 56.6 PSI MAX |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 應(yīng)用： | 系統(tǒng)基礎(chǔ)芯片 |
| 接口： | CAN，LIN |
| 電源電壓： | 5.5 V ~ 27 V |
| 封裝/外殼： | 32-BSOP（0.295"，7.50mm 寬）裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-SOICW 裸露焊盤 |
| 包裝： | 帶卷 (TR) |
| 安裝類型： | 表面貼裝 |
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Analog Integrated Circuit Device Data
72
Freescale Semiconductor
33903/4/5
SERIAL PERIPHERAL INTERFACE
DETAIL OF CONTROL BITS AND REGISTER MAPPING
Table 20. Initialization Miscellaneous Functions, INIT MISC (Note: Register can be written only in INIT mode)
MOSI First Byte [15-8]
[b_15 b_14] 0_1000 [P/N]
MOSI Second Byte, bits 7-0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
01 01_ 000 P
LPM w RNDM
SPI parity
INT pulse
INT width
INT flash
Dbg Res[2]
Dbg Res[1]
Dbg Res[0]
Default state
0
Condition for default
POR
Bit
Description
b7
LPM w RNDM - This enables the usage of random bits 2, 1 and 0 of the MODE register to enter into LP VDD OFF or LP VDD ON.
0
Function disable: the LP mode can be entered without usage of Random Code
1
Function enabled: the LP mode is entered using the Random Code
b6
SPI parity - Select usage of the parity bit in SPI write operation
0
Function disable: the parity is not used. The parity bit must always set to logic 0.
1
Function enable: the parity is used, and parity must be calculated.
b5
INT pulse -Select INT pin operation: low level pulse or low level
0
INT pin will assert a low level pulse, duration selected by bit [b4]
1
INT pin assert a permanent low level (no pulse)
b4
INT width - Select the INT pulse duration
0
INT pulse duration is typically 100
s. Ref. to dynamic parameter table for exact value.
1
INT pulse duration is typically 25
s. Ref. to dynamic parameter table for exact value.
b3
INT flash - Select INT pulse generation at 50% of the Watchdog Period in Flash mode
Function disable
Function enable: an INT pulse will occur at 50% of the Watchdog Period when device in Flash mode.
b2, b1, b0
Dbg Res[2], Dbg Res[1], Dbg Res[0] - Allow verification of the external resistor connected at DBG pin. Ref. to parametric table for resistor range
value.(40)
0xx
Function disable
100
100 verification enable: resistor at DBG pin is typically 68 kohm (RB3) - Selection of SAFE mode B3
101
101 verification enable: resistor at DBG pin is typically 33 kohm (RB2 - Selection of SAFE mode B2
110
110 verification enable: resistor at DBG pin is typically 15 kohm (RB1) - Selection of SAFE mode B1
111
111 verification enable: resistor at DBG pin is typically 0 kohm (RA) - Selection of SAFE mode A
Notes
40.
Bits b2,1 and 0 allow the following operation:
First, check the resistor device has detected at the DEBUG pin. If the resistor is different, bit 5 (Debug resistor) is set in INTerrupt
register (Ref. to device flag table).
Second, over write the resistor decoded by device, to set the SAFE mode operation by SPI. Once this function is selected by bit 2 = 1,
this selection has higher priority than “hardware”, and device will behave according to b2,b1 and b0 setting
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