BEHAVIOR AT POWER UP AND POWER DOWN " />
參數(shù)資料
型號(hào): MCZ33905BS3EK
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 51/106頁(yè)
文件大?。?/td> 0K
描述: IC SBC CAN HS 3.3V 32SOIC
標(biāo)準(zhǔn)包裝: 42
應(yīng)用: 系統(tǒng)基礎(chǔ)芯片
接口: CAN,LIN
電源電壓: 5.5 V ~ 28 V
封裝/外殼: 32-BSOP(0.295",7.50mm 寬)裸露焊盤
供應(yīng)商設(shè)備封裝: 32-SOICW 裸露焊盤
包裝: 管件
安裝類型: 表面貼裝
Analog Integrated Circuit Device Data
Freescale Semiconductor
49
33903/4/5
FUNCTIONAL DEVICE OPERATION
BEHAVIOR AT POWER UP AND POWER DOWN
BEHAVIOR AT POWER UP AND POWER DOWN
DEVICE POWER UP
This section describe the device behavior during ramp up,
and ramp down of VSUP/1, and the flexibility offered mainly by
the Crank bit and the two VDD undervoltage reset thresholds.
The figures below illustrate the device behavior during
VSUP/1 ramp up. As the Crank bit is by default set to 0, VDD is
enabled when VSUP/1 is above VSUP TH 1 parameters.
Figure 28. VDD Start-up Versus VSUP/1 Tramp
DEVICE POWER DOWN
The figures below illustrate the device behavior during
VSUP/1 ramp down, based on Crank bit configuration, and
VDD undervoltage reset selection.
Crank Bit Reset (INIT Watchdog Register, Bit 0 =0)
Bit 0 = 0 is the default state for this bit.
During VSUP/1 ramp down, VDD remain ON until device
enters in Reset mode due to a VDD undervoltage condition
(VDD < 4.6 V or VDD < 3.2 V typically, threshold selected by
the SPI). When device is in Reset, if VSUP/1 is below
“VSUP_TH1”, VDD is turned OFF.
Crank Bit Set (INIT Watchdog Register, Bit 0 =1)
The bit 0 is set by SPI write. During VSUP/1 ramp down,
VDD remains ON until device detects a POR and set
BATFAIL. This occurs for a VSUP/1 approx 3.0 V.
D1
VBAT
VSUP/1
VSUP_TH1
VSUP_NOMINAL (ex 12 V)
VDD NOMINAL (ex 5.0 V)
VDD
Gnd
VDD_START UP
VDD_OFF
90% VDD_START UP
10% VDD_START UP
VDD
VSUP/1
I_VDD
VSUP slew rate
3390X
VDD_UV TH (typically 4.65 V)
RST
1.0 ms
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