參數(shù)資料
型號: MD80C32-20SC
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, 20 MHz, MICROCONTROLLER, CDIP40
封裝: 0.600 INCH, CERAMIC, DIP-40
文件頁數(shù): 25/32頁
文件大小: 3152K
代理商: MD80C32-20SC
83
Atmel ATmega16/32/64/M1/C1 [DATASHEET]
7647K–AVR–12/13
12.6.3 Fast PWM Mode
The fast pulse width modulation or fast PWM mode (WGM02:0 = 3 or 7) provides a high frequency PWM waveform generation
option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to
TOP then restarts from BOTTOM. TOP is defined as 0xFF when WGM2:0 = 3, and OCR0A when WGM2:0 = 7. In non-inverting
compare output mode, the output compare (OC0x) is cleared on the compare match between TCNT0 and OCR0x, and set at
BOTTOM. In inverting compare output mode, the output is set on compare match and cleared at BOTTOM. Due to the single-
slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that use
dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC
applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total
system cost.
In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at
the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 12-6. The TCNT0 value is in the
timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted
PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0x and TCNT0.
Figure 12-6. Fast PWM Mode, Timing Diagram
The Timer/Counter overflow flag (TOV0) is set each time the counter reaches TOP. If the interrupt is enabled, the interrupt
handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the COM0x1:0 bits to two
will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM0x1:0 to three: Setting the
COM0A1:0 bits to one allows the OC0A pin to toggle on compare matches if the WGM02 bit is set. This option is not available
for the OC0B pin (see Table 12-6 on page 88). The actual OC0x value will only be visible on the port pin if the data direction for
the port pin is set as output. The PWM waveform is generated by setting (or clearing) the OC0x register at the compare match
between OCR0x and TCNT0, and clearing (or setting) the OC0x register at the timer clock cycle the counter is cleared (changes
from TOP to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0A register represents special cases when generating a PWM waveform output in the fast
PWM mode. If the OCR0A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. Setting
the OCR0A equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the
COM0A1:0 bits.)
1234567
TCNTn
(COMnx1:0 = 2)
(COMnx1:0 = 3)
OCnx
Period
OCRnx Update and
TOVn Interrupt Flag Set
OCRnx Interrupt
Flag Set
f
OCnxPWM
f
clk_I/O
N 256
-----------------
=
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