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參數(shù)資料
| 型號： | MD80C32-30/883:D |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 30 MHz, MICROCONTROLLER, CDIP40 |
| 文件頁數(shù)： | 9/91頁 |
| 文件大小： | 19688K |
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148
7679H–CAN–08/08
AT90CAN32/64/128
Depending on the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clk
T2). clkT2 can be generated from an external or internal clock source,
selected by the Clock Select bits (CS22:0). When no clock source is selected (CS22:0 = 0) the
timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of
whether clk
T2 is present or not. A CPU write overrides (has priority over) all counter clear or
count operations.
The counting sequence is determined by the setting of the WGM21 and WGM20 bits located in
the Timer/Counter Control Register (TCCR2A). There are close connections between how the
counter behaves (counts) and how waveforms are generated on the Output Compare output
OC2A. For more details about advanced counting sequences and waveform generation, see
The Timer/Counter Overflow Flag (TOV2) is set according to the mode of operation selected by
the WGM21:0 bits. TOV2 can be used for generating a CPU interrupt.
14.5
Output Compare Unit
The 8-bit comparator continuously compares TCNT2 with the Output Compare Register
(OCR2A). Whenever TCNT2 equals OCR2A, the comparator signals a match. A match will set
the Output Compare Flag (OCF2A) at the next timer clock cycle. If enabled (OCIE2A = 1), the
Output Compare Flag generates an Output Compare interrupt. The OCF2A flag is automatically
cleared when the interrupt is executed. Alternatively, the OCF2A flag can be cleared by software
by writing a logical one to its I/O bit location. The Waveform Generator uses the match signal to
generate an output according to operating mode set by the WGM21:0 bits and Compare Output
mode (COM2A1:0) bits. The max and bottom signals are used by the Waveform Generator for
handling the special cases of the extreme values in some modes of operation (“Modes of Oper-
Figure 14-4 shows a block diagram of the Output Compare unit.
Figure 14-4. Output Compare Unit, Block Diagram
The OCR2A Register is double buffered when using any of the Pulse Width Modulation (PWM)
modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double
buffering is disabled. The double buffering synchronizes the update of the OCR2A Compare
OCFnx (Int.Req.)
= (8-bit Comparator )
OCRnx
OCnx
DATA BUS
TCNTn
WGMn1:0
Waveform Generator
top
FOCn
COMnX1:0
bottom
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相關代理商/技術參數(shù) |
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