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4317K–AVR–03/2013
AT90PWM2/3/2B/3B
Bits 7:6 – COM0A1:0: Compare Match Output A Mode
These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0
bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A pin
must be set in order to enable the output driver.
When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the
WGM02:0 bit setting.
Table 14-2 shows the COM0A1:0 bit functionality when the WGM02:0 bits
are set to a normal or CTC mode (non-PWM).
Table 14-3 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM
mode.
Note:
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com-
for more details.
Table 14-4 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase cor-
rect PWM mode.
Note:
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com-
Bits 5:4 – COM0B1:0: Compare Match Output B Mode
Table 14-2.
Compare Output Mode, non-PWM Mode
COM0A1
COM0A0
Description
0
Normal port operation, OC0A disconnected.
0
1
Toggle OC0A on Compare Match
1
0
Clear OC0A on Compare Match
1
Set OC0A on Compare Match
Table 14-3.
Compare Output Mode, Fast PWM M
ode(1)COM0A1
COM0A0
Description
0
Normal port operation, OC0A disconnected.
01
WGM02 = 0: Normal Port Operation, OC0A Disconnected.
WGM02 = 1: Toggle OC0A on Compare Match.
1
0
Clear OC0A on Compare Match, set OC0A at TOP
1
Set OC0A on Compare Match, clear OC0A at TOP
Table 14-4.
Compare Output Mode, Phase Correct PWM Mode
COM0A1
COM0A0
Description
0
Normal port operation, OC0A disconnected.
01
WGM02 = 0: Normal Port Operation, OC0A Disconnected.
WGM02 = 1: Toggle OC0A on Compare Match.
10
Clear OC0A on Compare Match when up-counting. Set OC0A on
Compare Match when down-counting.
11
Set OC0A on Compare Match when up-counting. Clear OC0A on
Compare Match when down-counting.