參數(shù)資料
型號(hào)： MD80C32E-16SHXXX:D
廠商： ATMEL CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, 16 MHz, MICROCONTROLLER, CDIP40
封裝： CERAMIC, DIP-40
文件頁(yè)數(shù)： 20/28頁(yè)
文件大?。?/td> 6193K
27
2467X–AVR–06/11
ATmega128
The control bits for the External Memory Interface are located in three registers, the MCU Con-
trol Register – MCUCR, the External Memory Control Register A – XMCRA, and the External
Memory Control Register B – XMCRB.
When the XMEM interface is enabled, the XMEM interface will override the setting in the data
direction registers that corresponds to the ports dedicated to the XMEM interface. For details
about the port override, see the alternate functions in section “I/O Ports” on page 65. The XMEM
interface will auto-detect whether an access is internal or external. If the access is external, the
XMEM interface will output address, data, and the control signals on the ports according to Fig-
ure 13 (this figure shows the wave forms without wait-states). When ALE goes from high-to-low,
there is a valid address on AD7:0. ALE is low during a data transfer. When the XMEM interface
is enabled, also an internal access will cause activity on address, data and ALE ports, but the
RD and WR strobes will not toggle during internal access. When the External Memory Interface
is disabled, the normal pin and data direction settings are used. Note that when the XMEM inter-
face is disabled, the address space above the internal SRAM boundary is not mapped into the
internal SRAM. Figure 12 illustrates how to connect an external SRAM to the AVR using an octal
latch (typically “74 x 573” or equivalent) which is transparent when G is high.
Address Latch
Requirements
Due to the high-speed operation of the XRAM interface, the address latch must be selected with
care for system frequencies above 8MHz @ 4V and 4MHz @ 2.7V. When operating at condi-
tions above these frequencies, the typical old style 74HC series latch becomes inadequate. The
External Memory Interface is designed in compliance to the 74AHC series latch. However, most
latches can be used as long they comply with the main timing parameters. The main parameters
for the address latch are:
D to Q propagation delay (t
PD).
Data setup time before G low (t
SU).
Data (address) hold time after G low (
TH).
The External Memory Interface is designed to guaranty minimum address hold time after G is
asserted low of t
h = 5 ns. Refer to tLAXX_LD/tLLAXX_ST in “External Data Memory Timing” Tables
137 through Tables 144 on pages 328 - 330. The D-to-Q propagation delay (t
PD) must be taken
into consideration when calculating the access time requirement of the external component. The
data setup time before G low (t
SU) must not exceed address valid to ALE low (tAVLLC) minus PCB
wiring delay (dependent on the capacitive load).
Figure 12. External SRAM Connected to the AVR
D[7:0]
A[7:0]
A[15:8]
RD
WR
SRAM
DQ
G
AD7:0
ALE
A15:8
RD
WR
AVR
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