Interrupts
ARM DDI 0165B
Copyright 2000 ARM Limited. All rights reserved.
5-3
5.2
Hardware interface
The hardware interrupt is described under the following headings:
5.2.1
Generating an interrupt
You can make the ARM9E-S take the FIQ or IRQ exceptions (if interrupts are enabled
within the core) by asserting (LOW) the nFIQ or nIRQ inputs, respectively.
It is essential that once asserted, the interrupt input remains asserted until the ARM9E-S
has completed its interrupt exception entry sequence. When an interrupt input is
asserted, it must remain asserted until the ARM9E-S acknowledges to the source of the
interrupt that the interrupt has been taken. This acknowledgement normally occurs
when the interrupt service routine accesses the peripheral causing the interrupt, for
example:
by reading an interrupt status register in the systems interrupt controller
by writing to a clear interrupt control bit
by writing data to, or reading data from the interrupting peripheral.
5.2.2
Synchronization
The nFIQ and nIRQ inputs are synchronous inputs to the ARM9E-S, and must be setup
and held about the rising edge of the ARM9E-S clock, CLK. If interrupt events that are
asynchronous to CLK are present in a system, synchronization register(s) that are
external to the ARM9E-S are required.
5.2.3
Re-enabling interrupts after an interrupt exception
You must take care when re-enabling interrupts (for example at the end of an interrupt
routine or with a reentrant interrupt handler). You must ensure that the original source
of the interrupt has been removed before interrupts are enabled again on the ARM9E-S.
If you cannot guarantee this, the ARM9E-S might retake the interrupt exception
prematurely.
When considering the timing relation of removing the source of interrupt and
re-enabling interrupts on the ARM9E-S, you must take into account the pipelined
nature of the ARM9E-S and the memory system to which it is connected. For example,
the instruction that causes the removal of the interrupt request (that is, deassertion of