參數(shù)資料
型號(hào)： MD80C52CXXX-16P883D
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CDIP40
封裝： 0.600 INCH, CERAMIC, DIP-40
文件頁(yè)數(shù)： 26/32頁(yè)
文件大?。?/td> 3152K
代理商： MD80C52CXXX-16P883D
84
Atmel ATmega16/32/64/M1/C1 [DATASHEET]
7647K–AVR–12/13
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC0x to toggle its logical
level on each compare match (COM0x1:0 = 1). The waveform generated will have a maximum frequency of fOC0 = fclk_I/O/2 when
OCR0A is set to zero. This feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the output
compare unit is enabled in the fast PWM mode.
12.6.4 Phase Correct PWM Mode
The phase correct PWM mode (WGM02:0 = 1 or 5) provides a high resolution phase correct PWM waveform generation option.
The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to TOP and
then from TOP to BOTTOM. TOP is defined as 0xFF when WGM2:0 = 1, and OCR0A when WGM2:0 = 5. In non-inverting
Compare Output mode, the Output Compare (OC0x) is cleared on the compare match between TCNT0 and OCR0x while
upcounting, and set on the compare match while downcounting. In inverting output compare mode, the operation is inverted.
The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric
feature of the dual-slope PWM modes, these modes are preferred for motor control applications.
In phase correct PWM mode the counter is incremented until the counter value matches TOP. When the counter reaches TOP,
it changes the count direction. The TCNT0 value will be equal to TOP for one timer clock cycle. The timing diagram for the
phase correct PWM mode is shown on Figure 12-7. The TCNT0 value is in the timing diagram shown as a histogram for
illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line
marks on the TCNT0 slopes represent compare matches between OCR0x and TCNT0.
Figure 12-7. Phase Correct PWM Mode, Timing Diagram
The Timer/Counter overflow flag (TOV0) is set each time the counter reaches BOTTOM. The interrupt flag can be used to
generate an interrupt each time the counter reaches the BOTTOM value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the COM0x1:0
bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM0x1:0 to three:
Setting the COM0A0 bits to one allows the OC0A pin to toggle on compare matches if the WGM02 bit is set. This option is not
available for the OC0B pin (see Table 12-7 on page 88). The actual OC0x value will only be visible on the port pin if the data
direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC0x register at the
compare match between OCR0x and TCNT0 when the counter increments, and setting (or clearing) the OC0x register at
compare match between OCR0x and TCNT0 when the counter decrements. The PWM frequency for the output when using
phase correct PWM can be calculated by the following equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
123
TCNTn
(COMnx1:0 = 2)
(COMnx1:0 = 3)
OCnx
Period
TOVn Interrupt
Flag Set
OCRnx Update
OCnx Interrupt
Flag Set
f
OCnxPCPWM
f
clk_I/O
N 510
-----------------
=
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