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| 型號(hào)： | MD80C52CXXX-16SCD |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CDIP40 |
| 文件頁(yè)數(shù)： | 65/80頁(yè) |
| 文件大?。?/td> | 5152K |
| 代理商： | MD80C52CXXX-16SCD |
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265
XMEGA A [MANUAL]
8077I–AVR–11/2012
available configurations are shown in “No Multiplexing” on page 265 through “Multiplexing address byte 0, 1and 2” on
page 266. Table 24-1 on page 265 describes the SRAM interface signals.
Table 24-1. SRAM Interface signals.
24.5.1 No Multiplexing
When no multiplexing is used, there is a one-to-one connection between the EBI and the SRAM. No external address
latches are used.
Figure 24-3. Non-multiplexed SRAM connection.
24.5.2 Multiplexing address byte 0 and 1
When address byte 0 (A[7:0]) and address byte 1 (A[15:8]) are multiplexed, they are output from the same port, and the
ALE1 signal from the device controls the address latch.
Figure 24-4. Multiplexed SRAM connection using ALE1.
Signal
Description
CS
Chip Select
WE
Write Enable
RE
Read Enable
ALE[2:1]
Address Latch Enable
A[23:0]
Address
D[7:0]
Data bus
AD[7:0]
Combined Address and Data
EBI
SRAM
D[7:0]
A[7:0]
D[7:0]
A[7:0]
A[15:8]
A[21:16]
A[15:8]
A[21:16]
EBI
SRAM
D[7:0]
A[15:8]/
A[7:0]
ALE1
D
Q
G
D[7:0]
A[7:0]
A[15:8]
A[19:16]
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