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參數(shù)資料
| 型號： | MD80C52EXXX-20 |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CDIP40 |
| 封裝： | CERAMIC, DIP-40 |
| 文件頁數(shù)： | 45/80頁 |
| 文件大?。?/td> | 5152K |
| 代理商： | MD80C52EXXX-20 |
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245
XMEGA A [MANUAL]
8077I–AVR–11/2012
21.14 DMA Support
DMA support is available on UART, USRT, and master SPI mode peripherals. For details on different USART DMA
transfer triggers, refer to “Transfer Triggers” on page 52.
21.15 Register Description
21.15.1 DATA – Data register
The USART transmit data buffer register (TXB) and USART receive data buffer register (RXB) share the same I/O
address and is referred to as USART data register (DATA). The TXB register is the destination for data written to the
DATA register location. Reading the DATA register location returns the contents of the RXB register.
For 5-bit, 6-bit, or 7-bit characters, the upper unused bits will be ignored by the transmitter and set to zero by the receiver.
The transmit buffer can be written only when DREIF in the STATUS register is set. Data written to the DATA register
when DREIF is not set will be ignored by the USART transmitter. When data are written to the transmit buffer and the
transmitter is enabled, the transmitter will load the data into the transmit shift register when the shift register is empty.
The data are then transmitted on the TxD pin.
The receive buffer consists of a two-level FIFO. Always read STATUS before DATA in order to get the correct status of
the receive buffer.
21.15.2 STATUS – Status register
Bit 7 – RXCIF: Receive Complete Interrupt Flag
This flag is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (i.e., does
not contain any unread data). When the receiver is disabled, the receive buffer will be flushed, and consequently RXCIF
will become zero.
When interrupt-driven data reception is used, the receive complete interrupt routine must read the received data from
DATA in order to clear RXCIF. If not, a new interrupt will occur directly after the return from the current interrupt. This flag
can also be cleared by writing a one to its bit location.
Bit 6 – TXCIF: Transmit Complete Interrupt Flag
This flag is set when the entire frame in the transmit shift register has been shifted out and there are no new data in the
transmit buffer (DATA). TXCIF is automatically cleared when the transmit complete interrupt vector is executed. The flag
can also be cleared by writing a one to its bit location.
Bit 5 – DREIF: Data Register Empty Flag
This flag indicates whether the transmit buffer (DATA) is ready to receive new data. The flag is one when the transmit
buffer is empty and zero when the transmit buffer contains data to be transmitted that has not yet been moved into the
shift register. DREIF is set after a reset to indicate that the transmitter is ready. Always write this bit to zero when writing
the STATUS register.
Bit
7654
3210
+0x00
RXB[[7:0]
TXB[[7:0]
Read/Write
R/W
Initial Value
0
Bit
7654
3210
+0x01
RXCIF
TXCIF
DREIF
FERR
BUFOVF
PERR
–RXB8
Read/Write
R
R/W
R
R/W
Initial Value
0
1
0
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