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參數(shù)資料
| 型號： | MD80C52TXXX-36P883D |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CDIP40 |
| 封裝： | 0.600 INCH, CERAMIC, DIP-40 |
| 文件頁數(shù)： | 6/91頁 |
| 文件大小： | 19688K |
| 代理商： | MD80C52TXXX-36P883D |
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111
Atmel ATmega16/32/64/M1/C1 [DATASHEET]
7647K–AVR–12/13
Table 13-3 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the phase correct or the phase and
frequency correct, PWM mode.
Note:
1.
A special case occurs when OCRnA/OCRnB equals TOP and COMnA1/COMnB1 is set. See Section 13.8.4
“Phase Correct PWM Mode” on page 105 for more details.
Bit 1:0 – WGMn1:0: Waveform Generation Mode
Combined with the WGMn3:2 bits found in the TCCRnB register, these bits control the counting sequence of the counter, the
source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 13-4. Modes of
operation supported by the Timer/Counter unit are: normal mode (counter), clear timer on compare match (CTC) mode, and
three types of Pulse Width Modulation (PWM) modes (see Section 13. “16-bit Timer/Counter1 with PWM” on page 92).
Note:
1. The CTCn and PWMn1:0 bit definition names are obsolete. Use the
WGMn2:0 definitions. However, the functionality and
location of these bits are compatible with previous versions of the timer.
Table 13-3. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM(1)
COMnA1/COMnB1
COMnA0/COMnB0
Description
0
Normal port operation, OCnA/OCnB disconnected.
0
1
WGMn3:0 = 8, 9 10 or 11: Toggle OCnA on compare match, OCnB
disconnected (normal port operation). For all other WGM1 settings,
normal port operation, OC1A/OC1B disconnected.
1
0
Clear OCnA/OCnB on compare match when up-counting. Set
OCnA/OCnB on compare match when downcounting.
1
Set OCnA/OCnB on compare match when up-counting. Clear
OCnA/OCnB on compare match when downcounting.
Table 13-4. Waveform Generation Mode Bit Description(1)
Mode
WGMn3
WGMn2
(CTCn)
WGMn1
(PWMn1)
WGMn0
(PWMn0) Timer/Counter Mode of Operation
TOP
Update of
OCRn
x at
TOVn Flag
Set on
0
Normal
0xFFFF
Immediate
MAX
1
0
1
PWM, phase correct, 8-bit
0x00FF
TOP
BOTTOM
2
0
1
0
PWM, phase correct, 9-bit
0x01FF
TOP
BOTTOM
3
0
1
PWM, phase correct, 10-bit
0x03FF
TOP
BOTTOM
4
0
1
0
CTC
OCRnA
Immediate
MAX
5
0
1
0
1
Fast PWM, 8-bit
0x00FF
TOP
6
0
1
0
Fast PWM, 9-bit
0x01FF
TOP
7
0
1
Fast PWM, 10-bit
0x03FF
TOP
8
1
0
PWM, phase and frequency correct
ICRn
BOTTOM
9
1
0
1
PWM, phase and frequency correct
OCRnA
BOTTOM
10
1
0
1
0
PWM, phase correct
ICRn
TOP
BOTTOM
11
1
0
1
PWM, phase correct
OCRnA
TOP
BOTTOM
12
1
0
CTC
ICRn
Immediate
MAX
13
1
0
1
(Reserved)
–
14
1
0
Fast PWM
ICRn
TOP
15
1
Fast PWM
OCRnA
TOP
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