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參數(shù)資料
| 型號： | MD83C154CXXX-25/883 |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 25 MHz, MICROCONTROLLER, CDIP40 |
| 封裝： | 0.600 INCH, CERAMIC, DIP-40 |
| 文件頁數(shù)： | 84/298頁 |
| 文件大?。?/td> | 8529K |
| 代理商： | MD83C154CXXX-25/883 |
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174
ATmega8A [DATASHEET]
8159E–AVR–02/2013
21.6.6
Miscellaneous States
There are two status codes that do not correspond to a defined TWI state, see Table 21-9.
Status 0xF8 indicates that no relevant information is available because the TWINT Flag is not set. This occurs
between other states, and when the TWI is not involved in a serial transfer.
Status 0x00 indicates that a bus error has occurred during a Two-wire Serial Bus transfer. A bus error occurs when
a START or STOP condition occurs at an illegal position in the format frame. Examples of such illegal positions are
during the serial transfer of an address byte, a data byte, or an acknowledge bit. When a bus error occurs, TWINT
is set. To recover from a bus error, the TWSTO Flag must set and TWINT must be cleared by writing a logic one to
it. This causes the TWI to enter the not addressed Slave mode and to clear the TWSTO Flag (no other bits in
TWCR are affected). The SDA and SCL lines are released, and no STOP condition is transmitted.
21.6.7
Combining Several TWI Modes
In some cases, several TWI modes must be combined in order to complete the desired action. Consider for exam-
ple reading data from a serial EEPROM. Typically, such a transfer involves the following steps:
1.
The transfer must be initiated.
2.
The EEPROM must be instructed what location should be read.
3.
The reading must be performed.
4.
The transfer must be finished.
Note that data is transmitted both from Master to Slave and vice versa. The Master must instruct the Slave what
location it wants to read, requiring the use of the MT mode. Subsequently, data must be read from the Slave, imply-
ing the use of the MR mode. Thus, the transfer direction must be changed. The Master must keep control of the
bus during all these steps, and the steps should be carried out as an atomical operation. If this principle is violated
in a multimaster system, another Master can alter the data pointer in the EEPROM between steps 2 and 3, and the
Master will read the wrong data location. Such a change in transfer direction is accomplished by transmitting a
REPEATED START between the transmission of the address byte and reception of the data. After a REPEATED
START, the Master keeps ownership of the bus. The following figure shows the flow in this transfer.
Figure 21-17. Combining Several TWI Modes to Access a Serial EEPROM
21.7
Multi-master Systems and Arbitration
If multiple masters are connected to the same bus, transmissions may be initiated simultaneously by one or more
of them. The TWI standard ensures that such situations are handled in such a way that one of the masters will be
Table 21-9.
Miscellaneous States
Status Code
(TWSR)
Prescaler Bits
are 0
Status of the Two-wire Serial
Bus and Two-wire Serial Inter-
face Hardware
Application Software Response
Next Action Taken by TWI Hardware
To/from TWDR
To TWCR
STA
STO
TWINT
TWEA
0xF8
No relevant state information
available; TWINT = “0”
No TWDR action
No TWCR action
Wait or proceed current transfer
0x00
Bus error due to an illegal
START or STOP condition
No TWDR action
0
1
X
Only the internal hardware is affected, no STOP condi-
tion is sent on the bus. In all cases, the bus is released
and TWSTO is cleared.
Master Transmitter
Master Receiver
S = START
Rs = REPEATED START
P = STOP
Transmitted from master to slave
Transmitted from slave to master
S
SLA+W
A
ADDRESS
A
Rs
SLA+R
A
DATA
A
P
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