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參數(shù)資料
| 型號： | MD83C154CXXX-L16/883D |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CDIP40 |
| 文件頁數(shù)： | 33/232頁 |
| 文件大?。?/td> | 61013K |
| 代理商： | MD83C154CXXX-L16/883D |
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128
ATtiny25/45/85 [DATASHEET]
2586Q–AVR–08/2013
17.6
Changing Channel or Reference Selection
The MUX[3:0] and REFS[2:0] bits in the ADMUX Register are single buffered through a temporary register to which
the CPU has random access. This ensures that the channels and voltage reference selection only takes place at a
safe point during the conversion. The channel and voltage reference selection is continuously updated until a con-
version is started. Once the conversion starts, the channel and voltage reference selection is locked to ensure a
sufficient sampling time for the ADC. Continuous updating resumes in the last ADC clock cycle before the conver-
sion completes (ADIF in ADCSRA is set). Note that the conversion starts on the following rising ADC clock edge
after ADSC is written. The user is thus advised not to write new channel or voltage reference selection values to
ADMUX until one ADC clock cycle after ADSC is written.
If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special care must be taken
when updating the ADMUX Register, in order to control which conversion will be affected by the new settings.
If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the ADMUX Register is
changed in this period, the user cannot tell if the next conversion is based on the old or the new settings. ADMUX
can be safely updated in the following ways:
a.
When ADATE or ADEN is cleared.
b.
During conversion, minimum one ADC clock cycle after the trigger event.
c.
After a conversion, before the Interrupt Flag used as trigger source is cleared.
When updating ADMUX in one of these conditions, the new settings will affect the next ADC conversion.
17.6.1
ADC Input Channels
When changing channel selections, the user should observe the following guidelines to ensure that the correct
channel is selected:
In Single Conversion mode, always select the channel before starting the conversion. The channel selection may
be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the con-
version to complete before changing the channel selection.
In Free Running mode, always select the channel before starting the first conversion. The channel selection may
be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the first
conversion to complete, and then change the channel selection. Since the next conversion has already started
automatically, the next result will reflect the previous channel selection. Subsequent conversions will reflect the
new channel selection.
17.6.2
ADC Voltage Reference
The voltage reference for the ADC (V
REF) indicates the conversion range for the ADC. Single ended channels that
exceed V
REF will result in codes close to 0x3FF. VREF can be selected as either VCC, or internal 1.1V / 2.56V volt-
age reference, or external AREF pin. The first ADC conversion result after switching voltage reference source may
be inaccurate, and the user is advised to discard this result.
17.7
ADC Noise Canceler
The ADC features a noise canceler that enables conversion during sleep mode to reduce noise induced from the
CPU core and other I/O peripherals. The noise canceler can be used with ADC Noise Reduction and Idle mode. To
make use of this feature, the following procedure should be used:
Make sure that the ADC is enabled and is not busy converting. Single Conversion mode must be selected and
the ADC conversion complete interrupt must be enabled.
Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion once the CPU has been
halted.
If no other interrupts occur before the ADC conversion completes, the ADC interrupt will wake up the CPU and
execute the ADC Conversion Complete interrupt routine. If another interrupt wakes up the CPU before the ADC
相關PDF資料 |
PDF描述 |
|---|---|
| MD83C154XXX-16P883D | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CDIP40 |
| MR80C154-L16/883 | 8-BIT, 16 MHz, MICROCONTROLLER, CQCC44 |
| MR83C154TXXX-16/883 | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQCC44 |
| MR83C154TXXX-20/883 | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CQCC44 |
| MR80C154-25P883 | 8-BIT, 25 MHz, MICROCONTROLLER, CQCC44 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MD83C154-L16 | 制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
| MD83C154T-12 | 制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
| MD83C154T-16 | 制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
| MD83C154T-20 | 制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
| MD83C154T-25 | 制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
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