MDS108
Data Sheet
28
Zarlink Semiconductor Inc.
114
116
115
98
118
Port 8 Serial Interface
102
100
97
110
107
109
98
114
115
Miscellaneous Control Pins
95
148
125
M8_LINK
M8_SPEED
M8_DUPLEX
M8_COL
M8_REFCLK
I, U
I/O, U
I, U
I, U
I/O, U
Port 8 Link Status
Port 8 Speed Select (100 Mb = 1)
Port 8 Full Duplex Select (half duplex = 0)
Port 8 Collision Detect
Port 8 Reference Clock
S8_RXD
S8_RXCLK
S8_CRS_DV
S8_TXD
S8_TXCLK
S8_TXEN
S8_COL
S8_LINK
S8_DUPLEX
I, U
I, U
I, D
O
I
O
I, U
I, U
I, U
Port 8 Serial Receive Data
Port 8 Serial Receive Clock
Port 8 Serial Carrier Sense and Data Valid
Port 8 Serial Transmit Data
Port 8 Serial Transmit Clock
Port 8 Serial Transmit Enable
Port 8 Serial Collision Detect
Port 8 Link Status
Port 8 Full-Duplex Select (half duplex = 0)
M_CLK
SCLK
TEST#
I
I
I, U
Reference RMII Clock
System Clock (50 - 80 MHz)
Manufacturing Pin.
Leave as No Connect (NC)
Port Trunking Enable
Port Mirroring Control
Reset Pin
PHY Reset Pin
126
146, 145, 144, 143
142
141
Test Pins
139
TRUNK_EN
MIR_CTL[3:0]
RESIN#
RESETOUT#
I, D
I/O, U
I, S
O
TMODE#
I/O, U
Manufacturing Pin. Puts device into test
mode for ATE test.
Leave as No Connect (NC)
Test Outputs
Test Outputs
138, 137, 136, 135
134, 133, 132, 131
NC Pins
12, 13, 14, 15, 16, 17, 47, 48,
49, 50, 51, 52, 53, 54, 55, 56,
57, 58, 88, 89, 90, 91, 92, 93
Power Pins
3, 39, 73, 96, 130, 159, 184
11, 25, 59, 87, 101, 108, 119,
147, 152, 166, 175, 194, 202
18, 46, 80, 106, 140, 171, 198
7, 32, 66, 94, 99, 117, 121,
149, 154, 162, 180, 189, 207
TSTOUT[7:4]
TSTOUT[3:0]
O
I/O, U
N/C Reserved
No Connect
VDD (Core)
VDD
Input
Input
+3.3 Volt DC Supply for Core Logic (7 pins)
+3.3 Volt DC Supply for I/O Pads (13 pins)
VSS (Core)
VSS
Input
Input
Ground for Core Logic (7 pins)
Ground for I/O Pads (13 pins)
Pin No(s).
Symbol
Type
Name & Functions