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參數(shù)資料
| 型號(hào)： | MF180C51T-12D |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁(yè)數(shù)： | 92/170頁(yè) |
| 文件大?。?/td> | 4133K |
| 代理商： | MF180C51T-12D |
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28
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset
threshold voltage invokes the delay counter, which determines how long the device is kept in reset after V
CC rise.
The reset signal is activated again, without any delay, when V
CC decreases below the detection level.
Figure 8-2.
MCU Start-up, RESET Tied to V
CC
Figure 8-3.
MCU Start-up, RESET Extended Externally
8.2.2
V
CC Level Monitoring
ATtiny4/5/9/10 have a V
CC Level Monitoring (VLM) circuit that compares the voltage level at the VCC pin against
fixed trigger levels. The trigger levels are set with VLM2:0 bits, see “VLMCSR – VCC Level Monitoring Control and
The VLM circuit provides a status flag, VLMF, that indicates if voltage on the V
CC pin is below the selected trigger
level. The flag can be read from VLMCSR, but it is also possible to have an interrupt generated when the VLMF
status flag is set. This interrupt is enabled by the VLMIE bit in the VLMCSR register. The flag can be cleared by
changing the trigger level or by writing it to zero. The flag is automatically cleared when the voltage at V
CC rises
back above the selected trigger level.
The VLM can also be used to improve reset characteristics at falling supply. Without VLM, the Power-On Reset
(POR) does not activate before supply voltage has dropped to a level where the MCU is not necessarily functional
any more. With VLM, it is possible to generate a reset earlier.
When active, the VLM circuit consumes some power, as illustrated in Figure 17-48 on page 145. To save power
the VLM circuit can be turned off completely, or it can be switched on and off at regular intervals. However, detec-
tion takes some time and it is therefore recommended to leave the circuitry on long enough for signals to settle.
V
TIME-OUT
RESET
TOUT
INTERNAL
t
V
POT
V
RST
CC
V
TIME-OUT
TOUT
INTERNAL
CC
t
V
POT
V
RST
> t
RESET
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