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參數(shù)資料
| 型號： | MF1S5031XDUF |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 電源管理 |
| 英文描述： | MIFARE Classic 1K - Mainstream contactless smart card IC for fast and easy solution development |
| 中文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, UUC |
| 文件頁數(shù)： | 28/39頁 |
| 文件大小： | 685K |
| 代理商： | MF1S5031XDUF |
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MF1S50YYX
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.0 — 2 May 2011
196330
28 of 39
NXP Semiconductors
MF1S50yyX
MIFARE Classic 1K - Mainstream contactless smart card IC
14. Wafer specification
For more details on the wafer delivery forms see
Ref. 9
.
Table 29.
Wafer
diameter
maximum diameter after foil expansion
thickness
[1]
The step size and the gap between chips may vary due to changing foil expansion
[2]
Pads VSS and TESTIO are disconnected when wafer is sawn.
14.1 Fail die identification
Electronic wafer mapping covers the electrical test results and additionally the results of
mechanical/visual inspection. No ink dots are applied.
Wafer specifications MF1S50yyXDUy
200 mm typical (8 inches)
210 mm
120
μ
m
±
15
μ
m
75
μ
m
±
10
μ
m
not applicable
est. 66264
MF1S50yyXDUD
MF1S50yyXDUF
flatness
Potential Good Dies per Wafer (PGDW)
Wafer backside
material
treatment
roughness
Si
ground and stress relieve
R
a
max = 0.5
μ
m
R
t
max = 5
μ
m
Chip dimensions
step size
[1]
x = 659
μ
m
y = 694
μ
m
typical = 19
μ
m
minimum = 5
μ
m
gap between chips
[1]
Passivation
type
material
thickness
Au bump (substrate connected to VSS)
material
hardness
shear strength
height
height uniformity
sandwich structure
PSG / nitride
500 nm / 600 nm
> 99.9 % pure Au
35 to 80 HV 0.005
> 70 MPa
18
μ
m
within a die =
±
2
μ
m
within a wafer =
±
3
μ
m
wafer to wafer =
±
4
μ
m
minimum =
±
1.5
μ
m
LA, LB, VSS, TEST
[2]
= 66
μ
m
×
66
μ
m
±
5
μ
m
sputtered TiW
flatness
size
size variation
under bump metallization
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