參數(shù)資料
型號(hào)： MF280C31-12R
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, 12 MHz, MICROCONTROLLER, PQFP44
文件頁數(shù)： 137/170頁
文件大小： 4133K
代理商： MF280C31-12R
69
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
The extreme values for the OCR0x Register represents special cases when generating a PWM waveform output in
the phase correct PWM mode. If the OCR0x is set equal to BOTTOM the output will be continuously low and if set
equal to TOP the output will be set to high for non-inverted PWM mode. For inverted PWM the output will have the
opposite logic values.
11.9
Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clk
T0) is therefore shown as a clock enable signal
in the following figures. The figures include information on when interrupt flags are set, and when the OCR0x Reg-
ister is updated with the OCR0x buffer value (only for modes utilizing double buffering). Figure 11-12 on page 69
shows a timing diagram for the setting of OCF0x.
Figure 11-12. Timer/Counter Timing Diagram, Setting of OCF0x, no Prescaling
Figure 11-13 on page 69 shows the same timing data, but with the prescaler enabled.
Figure 11-13. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f
clk_I/O/8)
Figure 11-14 on page 70 shows the count sequence close to TOP in various modes. When using phase and fre-
quency correct PWM mode the OCR0x Register is updated at BOTTOM. The timing diagrams will be the same, but
clk
Tn
(clk
I/O/1)
OCFnx
clk
I/O
OCRnx
TCNTn
OCRnx Value
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCFnx
OCRnx
TCNTn
OCRnx Value
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
clk
I/O
clk
Tn
(clk
I/O/8)
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