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參數(shù)資料
| 型號： | MF280C31-30D |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 30 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁數(shù)： | 75/80頁 |
| 文件大小： | 5152K |
| 代理商： | MF280C31-30D |
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275
XMEGA A [MANUAL]
8077I–AVR–11/2012
24.9.5 SDRAMCTRLB – SDRAM Control register B
Bit 7:6 – MRDLY[1:0]: SDRAM Mode Register Delay
These bits select the delay between a LOAD MODE command and an ACTIVE command, in number of ClkPER2 cycles,
according to Table 24-14.
Table 24-14. SDRAM Load Mode to Active command delays settings.
Bit 5:3 – ROWCYCDLY[2:0]: SDRAM Row Cycle Delay
These bits select the delay between a REFRESH and an ACTIVE command in number of ClkPER2 cycles, according to
Table 24-15. SDRAM Row cycle delay settings.
Bit 2:0 – RPDLY[2:0]: SDRAM Row to Precharge Delay
RPDLY defines the delay between an Active command and a Precharge command in number of ClkPER2 cycles,
according to Table 24-16.
Bit
765
4
3
2
1
0
+0x08
MRDLY[1:0]
ROWCYCDLY[2:0]
RPDLY[2:0]
Read/Write
R/W
Initial Value
0
MRDLY[1:0]
Group configuration
Description
00
0CLK
Zero ClkPER2 cycles delay
01
1CLK
One ClkPER2 cycles delay
10
2CLK
Two ClkPER2 cycles delay
11
3CLK
Three ClkPER2 cycles delay
ROWCYDLY[2:0]
Group Configuration
Description
000
0CLK
Zero ClkPER2 cycles delay
001
1CLK
One ClkPER2 cycles delay
010
2CLK
Two ClkPER2 cycles delay
011
3CLK
Three ClkPER2 cycles delay
100
4CLK
Four ClkPER2 cycles delay
101
5CLK
Five ClkPER2 cycles delay
110
6CLK
Six ClkPER2 cycles delay
111
7CLK
seven ClkPER2 cycles delay
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