- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45322 > MF280C51-36D (ATMEL CORP) 8-BIT, MROM, 36 MHz, MICROCONTROLLER, PQFP44 PDF資料下載
參數(shù)資料
| 型號(hào)： | MF280C51-36D |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁(yè)數(shù)： | 133/170頁(yè) |
| 文件大?。?/td> | 4133K |
| 代理商： | MF280C51-36D |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)當(dāng)前第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)
65
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
The PWM frequency for the output can be calculated by the following equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR0x Register represents special cases when generating a PWM waveform output in
the fast PWM mode. If the OCR0x is set equal to BOTTOM (0x0000) the output will be a narrow spike for each
TOP+1 timer clock cycle. Setting the OCR0x equal to TOP will result in a constant high or low output (depending
on the polarity of the output set by the COM0x1:0 bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC0A to toggle
its logical level on each compare match (COM0A1:0 = 1). The waveform generated will have a maximum fre-
quency of f
0
A = fclk_I/O/2 when OCR0A is set to zero (0x0000). This feature is similar to the OC0A toggle in CTC
mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode.
11.8.4
Phase Correct PWM Mode
The phase correct Pulse Width Modulation or phase correct PWM mode (WGM03:0 = 1, 2, 3, 10, or 11) provides a
high resolution phase correct PWM waveform generation option. The phase correct PWM mode is, like the phase
and frequency correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOT-
TOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output
Compare (OC0x) is cleared on the compare match between TCNT0 and OCR0x while upcounting, and set on the
compare match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope
operation has lower maximum operation frequency than single slope operation. However, due to the symmetric
feature of the dual-slope PWM modes, these modes are preferred for motor control applications.
The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either ICR0 or
OCR0A. The minimum resolution allowed is 2-bit (ICR0 or OCR0A set to 0x0003), and the maximum resolution is
16-bit (ICR0 or OCR0A set to MAX). The PWM resolution in bits can be calculated by using the following equation:
In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed val-
ues 0x00FF, 0x01FF, or 0x03FF (WGM03:0 = 1, 2, or 3), the value in ICR0 (WGM03:0 = 10), or the value in
OCR0A (WGM03:0 = 11). The counter has then reached the TOP and changes the count direction. The TCNT0
value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown
on Figure 11-10 on page 66. The figure shows phase correct PWM mode when OCR0A or ICR0 is used to define
TOP. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The
diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes
represent compare matches between OCR0x and TCNT0. The OC0x interrupt flag will be set when a compare
match occurs.
f
OCnxPWM
f
clk_I/O
N1
TOP
+
-----------------------------------
=
R
PCPWM
TOP
1
+
log
2
log
-----------------------------------
=
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MF180C51T-12D | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP44 |
| MV80C51C-20R | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, PQFP44 |
| MV80C51T-30R | 8-BIT, MROM, 30 MHz, MICROCONTROLLER, PQFP44 |
| MT80C51C-20D | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, PQFP44 |
| MF280C51T-16D | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MF283C151C-12 | 制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
| MF283C151C-16 | 制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
| MF283C151C-20 | 制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
| MF283C151C-25 | 制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
| MF283C151C-30 | 制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。