參數(shù)資料
型號(hào)： MFR4300MAE40
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 10M bps, SERIAL COMM CONTROLLER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, 0.50 PITCH, LEAD FREE, MS-026BCD, LQFP-64
文件頁(yè)數(shù)： 34/266頁(yè)
文件大?。?/td> 1701K
代理商： MFR4300MAE40
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FlexRay Module (FLEXRAYV2)
MFR4300 Data Sheet, Rev. 3
Freescale Semiconductor
129
Message Buffer Control
11
CMT
Commit for Transmission — This bit applies only to transmit message buffers and indicates whether the
message buffer contains valid data that are ready for transmission. Both the application and the FlexRay module
can modify this bit.
Application: The application sets this bit to indicate that the transmit message buffer contains valid data ready
for transmission. The application clears this bit to indicate that the message buffer data are no longer valid for
transmission.
FlexRay module: The FlexRay module clears this bit when the message buffer data are no longer valid for
transmission.
0 Message buffer does not contain valid data.
1 Message buffer contains valid data.
10
EDT
Enable/Disable Trigger — This trigger bit is used to enable and disable a message buffer. The message buffer
enable is triggered when the application writes ‘1’ to this bit and the message buffer is disabled, i.e. the EDS
status bit is ‘0’. The message buffer disable is triggered when the application writes ‘1’ to this bit and the message
buffer is enabled, i.e. the EDS status bit is ‘1’.
0 No effect
1 message buffer enable/disable triggered
Note: If the application writes ‘1’ to this bit, the write access to all other bits is ignored.
9
LCKT
Lock/Unlock Trigger — This trigger bit is used to lock and unlock a message buffer. The message buffer lock is
triggered when the application writes ‘1’ to this bit and the message buffer is not locked, i.e. the LCKS status bit
is ‘0’. The message buffer unlock is triggered when the application writes ‘1’ to this bit and the message buffer is
locked, i.e. the LCKS status bit is ‘1’.
0 No effect
1 Trigger message buffer lock/unlock
Note: If the application writes ‘1’ to this bit and ‘0’ to the EDT bit, the write access to all other bits is ignored.
8
MBIE
Message Buffer Interrupt Enable — This control bit defines whether the message buffer will generate an
interrupt request when its MBIF flag is set.
0 Interrupt request generation disabled
1 Interrupt request generation enabled
Message Buffer Status
4
DUP
Data Updated — This status bit applies only to receive message buffers. It is always ‘0’ for transmit message
buffers. This bit provides information whether the frame header in the message buffer header field and the
message buffer data field were updated. See Section 3.4.6.3.4, “Message Buffer Status Update” for a detailed
description of the update condtions.
0 Frame Header and Message buffer data field not updated.
1 Frame Header and Message buffer data field updated.
3
DVAL
Data Valid — The semantic of this status bit depends on the message buffer type and transfer direction.
Receive Message Buffer: Indicates whether the message buffer data field contains valid frame data. See
Section 3.4.6.3.4, “Message Buffer Status Update” for a detailed update description of the update conditions.
0 message buffer data field contains no valid frame data
1 message buffer data field contains valid frame data
Single Transmit Message Buffer: Indicates whether the message is transferred again due to the state
transmission mode of the message buffer.
0 Message transferred for the first time.
1 Message will be transferred again.
Double Transmit Message Buffer: For the commit side it is always ‘0’. For the transmit side it indicates whether
the message is transferred again due to the state transmission mode of the message buffer.
0 Message transferred for the first time.
1 Message will be transferred again.
Table 3-75. MBCCSRn Field Descriptions (Sheet 2 of 3)
Field
Description
相關(guān)PDF資料
PDF描述
MG80C18612883B 16-BIT, 12.5 MHz, MICROPROCESSOR, CPGA68
MG80C186-10 16-BIT, 10 MHz, MICROPROCESSOR, CPGA68
MQ80C186-12 16-BIT, 12.5 MHz, MICROPROCESSOR, CQFP68
MII-266 32-BIT, 266 MHz, MICROPROCESSOR, CPGA296
MII-350 32-BIT, 350 MHz, MICROPROCESSOR, CPGA296
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MFR4-30K9FI 制造商:TT Electronics / Welwyn 功能描述: 制造商:Welwyn Components 功能描述: 制造商:TT Electronics / Welwyn 功能描述:Res Metal Film 30.9K Ohm 1% 1/4W ±100ppm/°C Conformal AXL Thru-Hole Ammo Pack
MFR4310E1MAE40 制造商:Freescale Semiconductor 功能描述:MFR4300 FLEXRAY - Trays
MFR4310FRDC 功能描述:子卡和OEM板 FLXRAY MFR4300 EVB RoHS:否 制造商:BeagleBoard by CircuitCo 產(chǎn)品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit
MFR4-330KFI 制造商:TT Electronics / Welwyn 功能描述:RESISTOR METAL FILM 330KOHM 500mW 1% 制造商:TT Electronics / Welwyn 功能描述:RESISTOR, METAL FILM, 330KOHM, 500mW, 1% 制造商:TT Electronics / Welwyn 功能描述:RESISTOR, METAL FILM, 330KOHM, 500mW, 1%; Product Range:WELWYN - MFR Series Metal Film Resistors; Resistance:330kohm; Power Rating:500mW; Resistance Tolerance: 1%; Resistor Case Style:Axial Leaded; Resistor Element Type:Metal Film ;RoHS Compliant: Yes
MFR4-330RFC 制造商:TT Electronics / Welwyn 功能描述:Res Metal Film 330 Ohm 1% 1/2W ±50ppm/°C Conformal AXL Thru-Hole Ammo Pack
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