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參數(shù)資料
| 型號(hào)： | MGCT04LH1S |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Transmit Circuit for TDMA/AMPS and CDMA/AMPS |
| 中文描述： | 發(fā)送電路的TDMA / AMPS二元和CDMA / AMPS二元 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 343K |
| 代理商： | MGCT04LH1S |
MGCT04
Preliminary Information
6
switched off in either of the sleep conditions shown
in Tables 4 and 5.
Active Low Pass Filter
The output from the quadrature modulator is passed
to the active low pass
fi
lter which attenuates wide
band noise and spurious outputs.
IF Variable Gain Amplifier
The
fi
ltered IF signal is passed to the IF variable gain
ampli
fi
er which in turn drives the single sideband
mixer. An externally applied AGC control voltage
allows the total circuit gain to be varied over a
minimum 84dB range.
The AGC action is split between the IF and RF
portions of the circuit and an internal AGC control
circuit processes the external AGC control voltage to
drive both IF and RF variable gain ampli
fi
ers and
provides a near linear control characteristic over the
entire AGC range.
Single Sideband Mixer
The modulated IF signal is fed to the single sideband
mixer which up-converts the IF to the RF frequency
to be transmitted by mixing with an RF signal from
one of two external UHF oscillator input pins,
seiected by an on chip multiplexer. When 1900MHz
mode is programmed with the VHF oscillator in
divide by four mode (Tables 4 and 5), the polarity of
the quadrature oscillator drive signals to the single
sideband mixer are reversed, thus selecting a low
side LO for 1900MHz PCS and high side for
900MHz. This technique allows a common IF and
fi
lter to be used for both 900MHz and 1900MHz
bands.
RF Variable Gain Amplifier
The SSB mixer is followed by the RF variable gain
ampli
fi
er stage which provides about 23dB of the
total gain variation. An additional SAW
fi
lter in the
transmit path is avoided by providing the gain
variation after the mixer.
The variable gain ampli
fi
er control circuit ensures
that the attenuation from maximum power is initially
controlled by the RF variable gain stage thus
reducing the noise contribution from the RF mixer.
Output Drivers
Separate output drive stages are provided for
900MHz and 1900MHz operation. A differential
design is used for both ampli
fi
ers to improve power
ef
fi
ciency and to ease power supply decoupling
problems. The 900MHz output stage provides a
linear output of 3 to 5 dBm for CDMA and 8 dBm for
TDMA operation, but is over-driven in AMPS mode to
obtain a typical output of 11dBm. In both power
driver stages the DC current is backed off as the RF
and IF gain is reduced, improving ef
fi
ciency when
less than maximum output power is required.
Control Inputs
Three control inputs are provided to select different
operating modes for the chip; the various modes
selected by the control pins are shown in Tables 4
and 5.
CP2
CP1
CP0
Function
0
0
0
Sleep mode. All circuits powered down
0
0
1
Quadrature modulator on. 1900MHz mode. Low side UHF LO. IF = VHF VCO
÷
4
0
1
0
Quadrature modulator on. 900MHz mode. high side UHF LO. IF = VHF VCO
÷
4
0
1
1
Standby mode. VHF oscillator input buffer, oscillator bias and divider on. All other
circuits powered down
Table 4 - Control pin functions; VHF LO in divide-by-four mode
CP2
CP1
CP0
Function
1
0
0
Sleep mode. All circuits powered down
1
0
1
Quadrature modulator on. 1900MHz mode. High side UHF LO. IF = VHF VCO
÷
2
1
1
0
Quadrature modulator on. 900MHz mode. high side UHF LO. IF = VHF VCO
÷
2
1
1
1
Standby mode. VHF oscillator input buffer, oscillator bias and divider on. All other
circuits powered down
Table 5 - Control pin functions; VHF LO in divide-by-two mode
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