參數(shù)資料
型號: MH16S64PHB-10
廠商: Mitsubishi Electric Corporation
英文描述: 1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
中文描述: 1073741824位(16777216 -文字,64位)SynchronousDRAM
文件頁數(shù): 23/52頁
文件大?。?/td> 1042K
代理商: MH16S64PHB-10
MH16S64AMA -8,-10,-12
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
( 23
MITSUBISHI
ELECTRIC
4. Mar.1997
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0127-0.0
[ Write Interrupted by Write ]
Burst write operation can be interrupted by new write of the same or the other bank.
Random column access is allowed. WRITE to WRITE interval is minimum 1 CK.
Write Interrupted by Write (BL=4)
CK
Command
A10
DQ
Write
Yi
0
0
Write
Yk
0
1
Dai0
Daj0
Daj1
Dbk0
Write
Yj
0
0
Dbk1 Dbk2
Write
Yl
0
0
Dal0
Dal1
Dal2
Dal3
[ Write Interrupted by Read ]
Burst write operation can be interrupted by read of the same or the other bank.
Random column access is allowed. WRITE to READ interval is minimum 1 CK. The
input data on DQ at the interrupting READ cycle is "don't care".
Write Interrupted by Read (BL=4, CL=3)
CK
Command
A10
DQ
Write
Yi
0
0
Qaj0
READ
Yj
0
0
Qaj1
Dai0
Dak0 Dak1
DQMB0-7
Write
Yk
0
0
READ
Yl
0
1
Qbl0
A0-9,11
BA0,1
A0-9,11
BA0,1
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