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參數資料
| 型號： | MH1M365CNXJ-5 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM |
| 中文描述： | 超頁模式37748736位（1048576 - Word的36位）動態(tài)隨機存儲器 |
| 文件頁數： | 5/15頁 |
| 文件大?。?/td> | 215K |
| 代理商： | MH1M365CNXJ-5 |
MITSUBISHI
ELECTRIC
( 5
HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM
MITSUBISHI LSIs
MH1M365CXJ/CNXJ-5,-6,-7
Oct.15.96
MIT-DS-0084-1.0
TIMING REQUIREMENTS (For Read, Write, Refresh, and Hyper-Page Mode Cycles)
(Ta=0 ~ 70°C, Vcc = 5V ± 10%, Vss=0V, unless otherwise noted See notes 14,15)
Note 14: The timing requirements are assumed t
T
=3ns.
15: V
IH(min)
and V
IL(max)
are reference levels for measuring timing of input signals.
16: t
RCD(max)
is specified as a reference point only. If t
RCD
is less than t
RCD(max),
access time is t
RAC.
If t
RCD
is greater than t
RCD(max),
access
time is controlled exclusively by t
CAC
or t
AA.
17: t
RAD(max)
is specified as a reference point only. If t
RAD
≤
t
RAD(max)
and t
ASC
≤
t
ASC(max),
access time is controlled exclusively by t
AA.
18: t
ASC(max)
is specified as a reference point only. If t
RCD
≥
t
RCD(max)
and t
ASC
≥
t
ASC(max),
access time is controlled exclusively by t
CAC.
19:
t
DZC
must be satisfied.
20: Either t
RDD
or
t
CDD
or t
ODD
must be satisfied.
21: t
T
is measured between V
IH(min)
and V
IL(max).
Read and Refresh Cycles
Note 22: Either t
RCH
or t
RRH
must be satisfied for a read cycle.
Parameter
Refresh cycle time
RAS high pulse width
Delay time, RAS low to CAS low
Symbol
Delay time, CAS high to RAS low
Delay time, RAS high to CAS low
CAS high pulse width
(Note21)
(Note16)
(Note17)
(Note18)
16.4
45
30
0
40
20
13
50
5
10
15
10
10
0
0
1
16.4
37
25
0
30
18
5
10
50
8
13
8
8
0
0
1
Column address delay time from RAS low
Row address setup time before RAS low
Column address setup time before CAS low
Row address hold time after RAS low
Column address hold time after CAS low
Delay time, data to CAS low
Transition time
(Note19)
(Note20)
(Note20)
Delay time, CAS high to data
0
0
15
13
Delay time, RAS high to data
15
13
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
Limits
Unit
Min
Max
Min
Max
Min
Max
16.4
50
35
0
50
20
13
50
5
10
15
10
10
0
0
1
0
20
20
Parameter
Read cycle time
RAS low pulse width
CAS low pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Symbol
0
Read Setup time before CAS low
Read hold time after CAS high
Read hold time after RAS high
Column address to RAS hold time
Column address to CAS hold time
(Note 22)
(Note 22)
0
10000
10000
10000
10000
90
50
8
40
13
10
25
13
0
0
110
60
10
48
15
10
30
18
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Limits
Unit
Min
Max
Min
Max
Min
130
70
13
55
20
Max
10000
10000
0
0
10
35
23
ns
ns
ns
ns
ns
t
REF
t
RP
t
RCD
t
CRP
t
RPC
t
CPN
t
RAD
t
ASR
t
ASC
t
RAH
t
CAH
t
DZC
t
RDD
t
CDD
t
T
t
RC
t
RAS
t
CAS
t
CSH
t
RSH
t
RCS
t
RCH
t
RRH
t
RAL
t
CAL
MH1M365C -5
MH1M365C -6
MH1M365C -7
MH1M365C -5
MH1M365C -6
MH1M365C -7
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| MH1M365CXJ-6 | HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM |
| MH1M365CNXJ-6 | HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM |
| MH1M365CXJ-7 | HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM |
| MH1M365CNXJ-7 | HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MH1M365CNXJ-6 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM |
| MH1M365CNXJ-7 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM |
| MH1M365CXJ-5 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM |
| MH1M365CXJ-6 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM |
| MH1M365CXJ-7 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM |
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