參數(shù)資料
型號(hào): MH1S64CWXTJ-15
廠商: Mitsubishi Electric Corporation
英文描述: 67108864-BIT (1048576-WORD BY 64-BIT)SynchronousDRAM
中文描述: 67108864位(1048576字,64位)SynchronousDRAM
文件頁(yè)數(shù): 21/45頁(yè)
文件大?。?/td> 683K
代理商: MH1S64CWXTJ-15
MH1S64CWXTJ-12,-15,-1539
67108864-BIT (1048576-WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
( 21
MITSUBISHI
ELECTRIC
Oct.28.1996
Some contents are subject to change without notice.
MIT-DS-0064-0.2
[ Write Interrupted by Write ]
Burst write operation can be interrupted by new write of the same or the other bank.
Random column access is allowed. WRITE to WRITE interval is minimum 1 CK.
Write Interrupted by Write (BL=4)
CK
Command
A0-9
A10
BA
DQ
Write
Yi
0
0
Write
Yk
0
1
Dai0
Daj0
Daj1
Dbk0
Write
Yj
0
0
Dbk1 Dbk2
Write
Yl
0
0
Dal0
Dal1
Dal2
Dal3
[ Write Interrupted by Read ]
Burst write operation can be interrupted by read of the same or the other bank.
Random column access is allowed. WRITE to READ interval is minimum 1 CK. The
input data on DQ at the interrupting READ cycle is "don't care".
Write Interrupted by Read (BL=4, CL=3)
CK
Command
A0-9
A10
BA
DQ
Write
Yi
0
0
Qaj0
READ
Yj
0
0
Qaj1
Dai0
Dak0 Dak1
DQMB0-7
Write
Yk
0
0
READ
Yl
0
1
Qbl0
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