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參數(shù)資料
| 型號： | MH2S64CWXTJ-12 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM |
| 中文描述： | 134217728位（2097152字，64位）SynchronousDRAM |
| 文件頁數(shù)： | 19/45頁 |
| 文件大?。?/td> | 691K |
| 代理商： | MH2S64CWXTJ-12 |
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MH2S64CZTJ/CWZTJ-12,-15,-1539
134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
( / 45 )
19
MITSUBISHI
ELECTRIC
Oct.28.1996
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0019-0.4
BURST INTERRUPTION
[ Read Interrupted by Read ]
Burst read option can be interrupted by new read of the same or the other bank. MH4S64CTJ
allows random column access. READ to READ interval is minimum 1 CK
Read Interrupted by Read (BL=4, CL=3)
CK
Command
A0-9
A10
BA
DQ
READ
Yi
0
0
READ
Yk
0
1
Qai0
Qaj1 Qbk0 Qbk1
READ
Yj
0
0
Qaj0
Qbk2
Qal0
READ
Yl
0
0
Qal1
Qal2
Qal3
[ Read Interrupted by Write ]
Burst read operation can be interrupted by write of the same or the other bank. Random
column access is allowed. In this case, the DQ should be controlled adequately by using the
DQMB0-7 to prevent the bus contention. The output is disabled automatically 2 cycle after
WRITE assertion.
Read Interrupted by Write (BL=4, CL=3)
CK
Command
A0-9
A10
BA
Q
READ
Yi
0
0
Qai0
Write
Yj
0
0
D
Daj0
Daj1
Daj2
Daj3
DQMB0-7
DQM control
Write control
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MH2S64CWXTJ-15 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM |
| MH2S64CWXTJ-1539 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM |
| MH2S64CWZTJ-12 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM |
| MH2S64CWZTJ-15 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM |
| MH2S64CWZTJ-1539 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM |
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