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參數(shù)資料
| 型號： | MH32D72AKLB-75 |
| 廠商： | Mitsubishi Electric Corporation |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:41; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:20; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:20-41 RoHS Compliant: No |
| 中文描述： | 2415919104位（33554432 - Word的72位），雙數(shù)據(jù)速率同步DRAM模塊 |
| 文件頁數(shù)： | 1/38頁 |
| 文件大小： | 327K |
| 代理商： | MH32D72AKLB-75 |
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MITSUBISHI LSIs
MITSUBISHI ELECTRIC
MH32D72AKLA-10,-75
2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0398-1.1
24.Nov.2000
Preliminary Spec.
Some contents are subject to change without notice.
1
DESCRIPTION
APPLICATION
Main memory unit for PC, PC server
FEATURES
Type name
133MHz
MH32D72AKLA-10
MH32D72AKLA-75
- Utilizes industry standard 32M X 4 DDR Synchronous DRAMs
in TSOP package , industry standard Registered Buffer in
TSSOP package , and industry standard PLL in TSSOP package.
-
Vdd=Vddq=2.5v±0.2V
- Double data rate architecture; two data transfers per
clock cycle
- Bidirectional, data strobe (DQS) is transmitted/received
with data
- Differential clock inputs (CLK and /CLK)
- data referenced to both edges of DQS
- /CAS latency- 2.0/2.5 (programmable)
- Burst length- 2/4/8 (programmable)
- Auto precharge / All bank precharge controlled by A10
- 4096 refresh cycles /64ms
- Auto refresh and Self refresh
- Row address A0-11 / Column address A0-9,11
- SSTL_2 Interface
- Module 1bank Configration
- Burst Type - sequential/interleave(programmable)
- Commands entered on each positive CLK edge
Max.
Frequency
100MHz
1pin
52pin
92pin
93pin
144pin
145pin
184pin
The MH32D72AKLA is 33554432 - word x 72-bit Double
Data Rate(DDR) Synchronous DRAM mounted module.
This consists of 18 industry standard 32M x 4 DDR
Synchronous DRAMs in TSOP with SSTL_2 interface which
achieves very high speed data rate up to 133MHz.
This socket-type memory module is suitable for main
memory in computer systems and easy to interchange or
add modules.
CLK
Access Time
[component level]
53pin
+ 0.75ns
+ 0.8ns
相關(guān)PDF資料 |
PDF描述 |
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| MH32D72KLH-10 | 2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| MH32D72KLH-75 | 2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| MH32S72AQJA-7 | ER 3C 3#16S PIN RECP |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MH32D72KLH-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| MH32D72KLH-75 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| MH32FAD | 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:8 pin DIP, 3.3 or 5.0 Volt, HCMOS/TTL Clock Oscillator |
| MH32FAD-R | 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:8 pin DIP, 3.3 or 5.0 Volt, HCMOS/TTL Clock Oscillator |
| MH32FAG | 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:8 pin DIP, 3.3 or 5.0 Volt, HCMOS/TTL Clock Oscillator |
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