- 您現在的位置：買賣IC網 > PDF目錄371106 > MH32S72PHB-7 (Mitsubishi Electric Corporation) 2415919104-BIT (33554432 - WORD BY 72-BIT)SynchronousDRAM PDF資料下載
參數資料
| 型號： | MH32S72PHB-7 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 2415919104-BIT (33554432 - WORD BY 72-BIT)SynchronousDRAM |
| 中文描述： | 2415919104位（33554432 - Word的72位）SynchronousDRAM |
| 文件頁數： | 4/56頁 |
| 文件大?。?/td> | 917K |
| 代理商： | MH32S72PHB-7 |
第1頁第2頁第3頁當前第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MH32S72AQJA-7, -8
17/Mar./2000
MIT-DS-0371-0.2
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MITSUBISHI
ELECTRIC
PIN FUNCTION
Input
Master Clock:All other inputs are referenced to the rising
edge of CK
CKE0
Input
Clock Enable:CKE controls internal clock.When CKE is
low,internal clock for the following cycle is ceased. CKE is
also used to select auto / self refresh. After self refresh
mode is started, CKE E becomes asynchronous input.Self
refresh is maintained as long as CKE is low.
/S0,2
Input
Chip Select: When /S is high,any command means
No Operation.
/RAS,/CAS,/W
Input
Combination of /RAS,/CAS,/W defines basic commands.
A0-11
Input
A0-11 specify the Row/Column Address in conjunction with
BA.The Row Address is specified by A0-11.The Column
Address is specified by A0-10.A10 is also used to indicate
precharge option.When A10 is high at a read / write
command, an auto precharge is performed. When A10 is
high at a precharge command, both banks are precharged.
Bank Address:BA0,1 is not simply BA.BA0,1 specifies
the bank to which a command is applied.BA must be set
with ACT,PRE,READ,WRITE commands
BA0-1
Input
DQ0-63
CB0-7
Input/Output
Data In and Data out are referenced to the rising edge
of CK
DQM0-7
Input
Din Mask/Output Disable:When DQMB is high in burst
write.Din for the current cycle is masked.When DQMB is
high in burst read,Dout is disabled at the next but one cycle.
Vdd,Vss
Power SupplyPower Supply for the memory mounted module.
CK0
REGE
Output
Register enable:When REGE is low,All control signals and
address are buffered. (Buffer mode) When REGE is
high,All control and address are latched. (Latch mode)
4
相關PDF資料 |
PDF描述 |
|---|---|
| MH32S72PHB-8 | 2415919104-BIT (33554432 - WORD BY 72-BIT)SynchronousDRAM |
| MH32S72QJA-7 | 2415919104-BIT ( 33554432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM |
| MH32S72APHB-6 | 2,415,919,104-BIT (33,554,432 - WORD BY 72-BIT)Synchronous DRAM |
| MH32S72APHB-7 | Aluminum Electrolytic Capacitor; Capacitor Type:General Purpose; Voltage Rating:16VDC; Capacitor Dielectric Material:Aluminum Electrolytic; Operating Temperature Range:-55 C to +105 C; Capacitance:6900uF RoHS Compliant: Yes |
| MH32S72APHB-8 | Aluminum Electrolytic Capacitor; Capacitor Type:General Purpose; Voltage Rating:100VDC; Capacitor Dielectric Material:Aluminum Electrolytic; Operating Temperature Range:-55 C to +105 C; Capacitance:78uF RoHS Compliant: Yes |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MH32S72PHB-8 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:2415919104-BIT (33554432 - WORD BY 72-BIT)SynchronousDRAM |
| MH32S72QJA-7 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:2415919104-BIT ( 33554432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM |
| MH32S72QJA-8 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:2415919104-BIT ( 33554432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM |
| MH32S72VJA-6 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM |
| MH32TAD | 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:8 pin DIP, 3.3 or 5.0 Volt, HCMOS/TTL Clock Oscillator |
發(fā)布緊急采購，3分鐘左右您將得到回復。