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參數(shù)資料
| 型號： | MH4M36CJD-5 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | FAST PAGE MODE ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM |
| 中文描述： | 快速頁面模式（4194304 - Word的36位）動態(tài)隨機(jī)存儲器 |
| 文件頁數(shù)： | 4/14頁 |
| 文件大?。?/td> | 130K |
| 代理商： | MH4M36CJD-5 |
MITSUBISHI
ELECTRIC
( 4
FAST PAGE MODE ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM
MH4M36CJD-5,-6,-7
MITSUBISHI LSIs
Jun/17/1996
MIT-DS-0035-0.0
SWITCHING CHARACTERISTICS
(Ta=0 ~ 70 °C, Vcc=5V ± 10%, Vss=0V, unless otherwise noted , see notes 5,12,13)
Note 5: An initial pause of 500us is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles
containing a RAS clock such as RAS-Only refresh).
Note the RAS may be cycled during the initial pause . And any 8 RAS or RAS/CAS cycles are required after prolonged periods
(greater than 32 ms) of RAS inactivity before proper device operation is achieved.
6: Measured with a load circuit equivalent to 2TTL loads and 100pF.
7: Assumes that tRCD
≥
tRCD(max) and tASC
≥
tASC(max).
8: Assumes that tRCD
≤
tRCD(max) and tRAD
≤
tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table,
tRAC will increase by amount that tRCD exceeds the value shown.
9: Assumes that tRAD
≥
tRAD(max) and tASC
≤
tASC(max).
10: Assumes that tCP
≤
tCP(max) and tASC
≥
tASC(max).
11: tOFF(max) and tOEZ (max) defines the time at which the output achieves the high impedance state ( | IOUT |
≤
10 uA) and is not reference to
VOH(min) or VOL(max).
Limits
Min
Max
32
Parameter
Refresh cycle time
RAS high pulse width
Delay time, RAS low to CAS low
Symbol
t
REF
t
RP
t
RCD
Unit
Min
Max
32
Min
Max
32
MH4M36CJD-5
MH4M36CJD-6
MH4M36CJD-7
ms
ns
ns
ns
ns
ns
ns
ns
t
CRP
t
RPC
t
CPN
Delay time, CAS high to RAS low
Delay time, RAS high to CAS low
CAS high pulse width
(Note19)
(Note14)
(Note15)
(Note16)
ns
ns
ns
ns
50
35
10
50
45
30
0
40
20
10
10
50
10
15
10
15
0
0
1
37
25
0
30
18
10
10
50
10
13
8
13
0
0
1
0
50
20
10
10
15
10
15
0
0
1
t
RAD
t
ASR
t
ASC
t
RAH
t
CAH
t
DZC
t
CDD
t
T
Column address delay time from RAS low
Row address setup time before RAS low
Column address setup time before CAS low
Row address hold time after RAS low
Column address hold time after CAS low
Delay time, data to CAS low
Delay time, CAS high to data
Transition time
TIMING REQUIREMENTS (For Read, Write,Refresh, and Fast-Page Mode Cycles)
(Ta=0 ~ 70 °C, Vcc=5V ± 10%, Vss=0V, unless otherwise noted See notes 12,13)
Limits
Min
Max
13
50
Parameter
Access time from CAS
Access time from RAS
Columu address access time
Access time from CAS precharge
Output low impedance time from CAS low
Output disable time after CAS high
Symbol
t
CAC
Unit
Min
Max
15
60
Min
Max
20
70
MH4M36CJD-5
MH4M36CJD-6
MH4M36CJD-7
ns
ns
ns
ns
ns
ns
0
5
0
5
0
5
35
40
15
30
35
15
25
30
13
t
RAC
t
AA
t
CPA
t
CLZ
t
OFF
(Note 6,7)
(Note 6,8)
(Note 6,9)
(Note 6,10)
(Note 6)
(Note 11)
(Note17)
(Note18)
0
0
0
15
13
15
ns
ns
Note 12: The timing requirements are assumed tT =5ns.
13: VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
14: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access
time is controlled exclusively by tCAC or tAA. tRCD(min) is specified as tRCD(min) =tRAH(min) +2tH+tASC(min).
15: tRAD(max) is specified as a reference point only. If tRAD
≥
tRAD(max) and tASC
≤
tASC(max), access time is controlled exclusively by tAA.
16: tASC(max) is specified as a reference point only. If tRCD
≥
tRCD(max) and tASC
≥
tASC(max), access time is controlled exclusively by tCAC.
17: Either tDZC or tDZO must be satisfied.
18: Either tCDD or tODD must be satisfied.
19: tT is measured between VIH(min) and VIL(max).
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| MH4M36CJD-6 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:FAST PAGE MODE ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM |
| MH4M36CJD-7 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:FAST PAGE MODE ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM |
| MH4M36DJD-7 | 制造商:Mitsubishi Electric 功能描述: |
| MH4S64BBKG-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM |
| MH4S64BBKG-10L | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM |
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