參數(shù)資料
型號(hào)： MH4V64AXJJ-6S
廠商： Mitsubishi Electric Corporation
英文描述： FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
中文描述： 快速頁面模式268435456位（4194304字，64位）動(dòng)態(tài)隨機(jī)存儲(chǔ)器
文件頁數(shù)： 13/25頁
文件大小： 217K
代理商： MH4V64AXJJ-6S
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
MITSUBISHI
ELECTRIC
( / 25 )
13
MITSUBISHI LSIs
Preliminary
Some of contents are subject
to change without notice.
MIT-DS-0072-0.5
26/Feb./1997
Fast Page Mode Cycle (Read, Early Write, Read -Write, Read-Modify-Write Cycle)
(Note 24)
Note 24: All previously specified timing requirements and switching characteristics are applicable to their respective Fast page mode cycle.
25: tRAS(min) is specified as two cycles of /CAS input are performed.
26: tCP(max) is specified as a reference point only.If tCP
≥
tCP(max),access time is controlled exclusively by tCAC.
Limits
Parameter
Symbol
Min
40
75
Max
(Note25)
(Note26)
15
100000
/CAS before /RAS Refresh Cycle
(Note 27)
Limits
Parameter
Symbol
Unit
Min
Max
Note 27: Eight or more /CAS before /RAS cycles instead of eight /RAS cycles are necessary for proper operation of /CAS before /RAS
refresh mode.
-6,-6S
-6,-6S
Unit
ns
ns
ns
ns
ns
ns
tPC
tPRWC
tRAS
tCP
tCPRH
tCPWD
Hyper page mode read/write cycle time
Hyper page mode read write/read modify write cycle time
/RAS low pulse width for read write cycle
/CAS high pulse width
/RAS hold time after /CAS precharge
Delay time, /CAS precharge to /W low
35
35
100
10
(Note23)
ns
ns
ns
ns
tCSR
tCHR
tRSR
tRHR
/CAS setup time before /RAS low
/CAS hold time after /RAS low
Read setup time before /RAS low
Read hold time after /RAS low
10
10
5
-5,-5S
Min
35
70
Max
10
125000
30
30
85
5
-5,-5S
Min
5
Max
10
10
10
10
Read-Write and Read-Modify-Write Cycles
Limits
Parameter
Symbol
Unit
Min
150
95
Max
-6,-6S
(Note22)
(Note23)
(Note23)
(Note23)
Read write/read modify write cycle time
/RAS low pulse width
/CAS low pulse width
/CAS hold time after /RAS low
/RAS hold time after /CAS low
Read setup time before /CAS low
Delay time, /CAS low to /W low
Delay time, /RAS low to /W low
Delay time, address to /W low
/CAS hold time after /W low
/RAS hold time after /W low
Write pulse width
Data setup time before /W low
Date hold time after /W low
/OE hold time after /W low
tRWC
tRAS
tCAS
tCSH
tRSH
tRCS
tCWD
tRWD
tAWD
tCWL
tRWL
tWP
tDS
tDH
tOEH
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10000
10000
50
0
30
75
45
15
15
10
0
10
15
50
95
Note 22: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT.
23:tWCS, tCWD,tRWD ,tAWD and,tCPWD are specified as reference points only. If tWCS
≥
tWCS(min) the cycle is an early write cycle
and the DQ pins will remain high impedance throughout the entire cycle. If tCWD
≥
tCWD(min), tRWD
≥
tRWD (min), tAWD
≥
tAWD(min)
and tCPWD
≥
tCPWD(min) (for Fast page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the
data read from the selected address. If neither of the above condition (delayed write) is satisfied,the DQ (at access time and until
/CAS or /OE goes back to VIH) is indeterminate.
Min
130
85 10000
10000
Max
-5,-5S
50
0
30
65
40
15
15
10
0
10
10
50
85
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