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| 型號： | MH4V724AWXJ-5 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | FAST PAGE MODE 301989888 - BIT ( 4194304 - WORD BY 72 - BIT ) DYNAMIC RAM |
| 中文描述： | 快速頁面模式301989888 -位（4194304 - Word的72 -位）動態(tài)隨機存儲器 |
| 文件頁數(shù)： | 9/20頁 |
| 文件大?。?/td> | 174K |
| 代理商： | MH4V724AWXJ-5 |
MITSUBISHI LSIs
MH4V724AWXJ -5, -6
Preliminary Spec.
Specifications subject to
change without notice.
MITSUBISHI
ELECTRIC
( / 20 )
9
26/Feb./1997
FAST PAGE MODE 301989888 - BIT ( 4194304 - WORD BY 72 - BIT ) DYNAMIC RAM
MIT-DS-0119-0.0
Fast Page Mode Cycle (Read, Early Write, Read -Write, Read-Modify-Write Cycle) (Note 24)
Note 24: All previously specified timing requirements and switching characteristics are applicable to their respective Fast page mode cycle.
26: tCP(max) is specified as a reference point only. If tCP
≥
tCP(max),access time is controlled exclusively by tCAC.
Limits
Parameter
Symbol
Min
40
85
Max
(Note25)
(Note26)
15
51200
/CAS before /RAS Refresh Cycle (Note 27)
Limits
Parameter
Symbol
Unit
Min
10
10
Max
Note 27: Eight or more /CAS before /RAS cycles instead of eight /RAS cycles are necessary for proper operation of /CAS before /RAS refresh
-6
-6
Unit
ns
ns
ns
ns
ns
ns
tPC
tPRWC
tRAS
tCP
tCPRH
tCPWD
Fast page mode read/write cycle time
Fast page mode read write/read modify write cycle time
/RAS low pulse width for read write cycle
/CAS high pulse width
/RAS hold time after /CAS precharge
Delay time, /CAS precharge to W low
35
60
100
10
(Note23)
ns
ns
ns
ns
tCSR
tCHR
tRSR
tRHR
/CAS setup time before /RAS low
/CAS hold time after /RAS low
Read setup time before /RAS low
Read hold time after /RAS low
10
10
Min
35
76
Max
10
51200
-5
30
53
85
8
Min
10
10
Max
-5
10
10
Read-Write and Read-Modify-Write Cycles
Limits
Parameter
Symbol
Unit
Min
155
105
Max
-6
(Note22)
(Note23)
(Note23)
(Note23)
Read write/read modify write cycle time
/RAS low pulse width
/CAS low pulse width
/CAS hold time after /RAS low
/RAS hold time after /CAS low
Read setup time before /CAS low
Delay time, /CAS low to /W low
Delay time, /RAS low to /W low
Delay time, address to /W low
/CAS hole time after /W low
/RAS hold time after /W low
Write pulse width
Data setup time before /W loe
Data hold time after /W low
tRWC
tRAS
tCAS
tCSH
tRSH
tRCS
tCWD
tRWD
tAWD
tCWL
tRWL
tWP
tDS
tDH
tOEH
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10000
10000
60
0
40
85
55
15
15
10
0
10
15
60
105
Note 22: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+5tT.
23:tWCS, tCWD,tRWD ,tAWD and,tCPWD are specified as reference points only. If tWCS
≥
tWCS(min) the cycle is an early write cycle and the DQ pins will remain
high impedance throughout the entire cycle. If tCWD
≥
tCWD(min), tRWD
≥
tRWD (min), tAWD
≥
tAWD(min) and tCPWD
≥
tCPWD(min) (for Fast page mode cycle only),
the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) is
satisfied,the DQ (at access time and until /CAS or /OE goes back to VIH) is indeterminate.
Min
131
91
Max
-5
10000
10000
54
0
36
73
48
15
15
10
0
10
13
54
91
/OE hold time after /W low
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