- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371108 > MH8S64BALD-6 (Mitsubishi Electric Corporation) 536,870,912-BIT ( 8,388,608-WORD BY 64-BIT ) Synchronous DYNAMIC RAM PDF資料下載
參數(shù)資料
| 型號： | MH8S64BALD-6 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 536,870,912-BIT ( 8,388,608-WORD BY 64-BIT ) Synchronous DYNAMIC RAM |
| 中文描述： | 536870912位（8388608字，64位）同步動態(tài)隨機存儲器 |
| 文件頁數(shù)： | 18/55頁 |
| 文件大?。?/td> | 588K |
| 代理商： | MH8S64BALD-6 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁當(dāng)前第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁
MH8S64PHC -7,-8,-10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
( / 55 )
18
MITSUBISHI
ELECTRIC
9/ Dec. /1998
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0282-0.0
Bank Activation and Precharge All (BL=4, CL=3)
CLK
Command
A0-9
A10
BA0,1
DQ
ACT
Xa
Xa
00
READ
Y
0
00
Qa0
Qa1
Qa2
Qa3
ACT
Xb
Xb
01
PRE
tRRD
tRCD
1
ACT
Xb
Xb
01
Precharge all
tRAS
tRP
OPERATION DESCRIPTION
BANK ACTIVATE
The SDRAM has four independent banks. Each bank is activated by the ACT command with
the bank address(BA0,1). A row is indicated by the row address A11-0. The minimum
activation interval between one bank and the other bank is tRRD.The number of banks which
are active concurrently is not limited.
PRECHARGE
The PRE command deactivates indicated by BA. When both banks are active, the precharge
all command(PREA,PRE + A10=H) is available to deactivate them at the same time. After tRP
from the precharge, an ACT command can be issued.
READ
After tRCD from the bank activation, a READ command can be issued. 1st output date is
available after the /CAS Latency from the READ, followed by (BL-1) consecutive date when
the Burst Length is BL. The start address is specified by A8-0, and the address sequence of
burst data is defined by the Burst Type. A READ command may be applied to any active bank,
so the row precharge time(tRP) can be hidden behind continuous output data(in case of BL=8)
by interleaving the dual banks. When A10 is high at a READ command, the
auto-precharge(READA) is performed. Any command (READ, WRITE, PRE, ACT) to the
same bank is inhibited till the internal precharge is complete. The internal precharge start at
BL after READA. The next ACT command can be issued after (BL + tRP) from the previous
READA.
A11
Xa
Xb
Xb
tRCmin
2ACT command/tRCmin
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MH8S64BALD-7 | 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM |
| MH8S64BALD-8 | 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM |
| MH8S64BBKD-10 | 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM |
| MH8S64BBKD-10L | 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM |
| MH8S64BBKG-10 | 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MH8S64BALD-7 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM |
| MH8S64BALD-8 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM |
| MH8S64BBKD-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM |
| MH8S64BBKD-10L | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM |
| MH8S64BBKG-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。