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參數資料
| 型號： | MH8S64BBKG-8L |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM |
| 中文描述： | 536870912位（8388608 -文字，64位）SynchronousDRAM |
| 文件頁數： | 26/55頁 |
| 文件大小： | 588K |
| 代理商： | MH8S64BBKG-8L |
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MH8S64PHC -7,-8,-10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
( / 55 )
26
MITSUBISHI
ELECTRIC
9/ Dec. /1998
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0282-0.0
[ Write Interrupted by Precharge ]
Burst write operation can be interrupted by precharge of the same bank. Random
column access is allowed. Because the write recovery time(tWR) is required from the
last data to PRE command.
Write Interrupted by Precharge (BL=4)
CK
Command
A10
DQ
Write
Yi
0
00
PRE
0
00
Dai0
Dai1
DQMB0-7
ACT
Xb
Xb
00
tWR
tRP
A0-9,11
BA0,1
A11
Xb
Dai2
[ Write Interrupted by Burst Terminate ]
A burst terminate command TBST can terminate burst write operation. In this case,
the write recovery time is not required and the bank remains active (Please see the
waveforms below).The WRITE to TBST minimum interval is 1CK.
Write Interrupted by Burst Terminate (BL=4)
CK
Command
A10
DQ
Write
Yi
0
0
TBST
Dai0
Dai1
DQMB0-7
Dai2
A0-9
BA0,1
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MH8S64BMG-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM |
| MH8S64BMG-7 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM |
| MH8S64BMG-8 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM |
| MH8S64DALD-6 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM |
| MH8S64DALD-7 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM |
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