參數資料
型號: MH8S64QFC-8L
廠商: Mitsubishi Electric Corporation
英文描述: 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
中文描述: 536870912位(8388608 -文字,64位)SynchronousDRAM
文件頁數: 30/55頁
文件大小: 588K
代理商: MH8S64QFC-8L
MH8S64PHC -7,-8,-10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
( 30
MITSUBISHI
ELECTRIC
9/ Dec. /1998
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0282-0.0
DQM CONTROL
DQMB0-7 is a dual function signal defined as the data mask for writes and the output
disable for reads. During writes, DQMB0-7 masks input data word by word. DQMB0-7
to write mask latency is 0.
During reads, DQMB0-7 forces output to Hi-Z word by word. DQMB0-7 to output Hi-Z
latency is 2.
DQM Function
CK
Command
DQ
Write
D0
D2
D3
DQMB0-7
READ
Q0
Q1
Q3
masked by DQM=H
disabled by DQM=H
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