參數(shù)資料
型號: MH8S72DCFD-6
廠商: Mitsubishi Electric Corporation
英文描述: 603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
中文描述: 603979776位(8,388,608 - Word的72位)同步動態(tài)隨機存儲器
文件頁數(shù): 18/56頁
文件大小: 732K
代理商: MH8S72DCFD-6
MITSUBISHI
ELECTRIC
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MH8S72BAFD -7, -8
MITSUBISHI LSIs
Preliminary
Spec.
1/ Dec./1998
MIT-DS-0273-0.2
AC TIMING REQUIREMENTS
(Ta=0 ~ 70°C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted)
Input Pulse Levels: 0.8V to 2.0V
Input Timing Measurement Level: 1.4V
CK
Signal
1.4V
1.4V
Any AC timing is
referenced to the input
signal crossing through
1.4V.
LATCH MODE
18
Limits
Symbol Parameter
-7
Unit
Min.
10
Max.
tCLK
CK cycle time
ns
ns
tCH
tCL
tT
tIS
tIH
tRC
tRCD
tRAS
tRP
tWR
tRRD
tCCD
tRSC
tSRX
CK High pulse width
CK Low pilse width
Transition time of CK
Input Setup time(all inputs)
Input Hold time(all inputs)
Row cycle time
Row to Column Delay
Row Active time
Row Precharge time
Write Recovery time
Act to Act Deley time
Col to Col Delay time
Mode Register Set Cycle time
Self Refresh Exit time
3
3
1
2
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
70
20
50
20
10
20
10
20
10
100000
tREF
Note:1 The timing requirements are assumed tT=1ns. If tT is longer than 1ns, (tT-1)ns
should be added to the parameter.
Refresh Interval time
64
ms
CL=3
CL=4
-8
Min.
13
Max.
4
4
1
2
0
10
70
20
50
20
10
20
10
20
10
100000
64
10
10
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