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參數(shù)資料
| 型號(hào)： | MIC2045 |
| 廠商： | Micrel Semiconductor,Inc. |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | SINGLE CHANNEL HIGH CURRENT LOW VOLTAGE, PROTECTED POWER DISTRIBUTION SWITCH |
| 中文描述： | 單聲道高當(dāng)前的低電壓，保護(hù)配電開關(guān) |
| 文件頁數(shù)： | 3/15頁 |
| 文件大?。?/td> | 269K |
| 代理商： | MIC2045 |
October 2003
3
MIC2044/2045
MIC2044/2045
Pin Description
Micrel
Pin Number
Pin Name
Pin Function
1
PWRGD
Power-Good (Output): Open drain N-Channel device, active high. This pin
asserts high when the voltage at PGREF exceeds its threshold.
2
EN
Switch Enable (Input): Gate control pin of the output MOSFET available as
an active high (
–
1) or active low (
–
2) input signal.
3
/FAULT
Fault Status (Output): Open drain N-Channel device, active low. This pin
indicates an overcurrent or thermal shutdown condition. For an overcurrent
event, /FAULT is asserted if the duration of the overcurrent condition lasts
longer than 32ms.
10
GND
Ground connection: Tie to analog ground.
4
SLEW
Slew-Rate Control (Input): A capacitor connected between this pin and
ground will reduce (slow) the output slew-rate. The output turn-on time must
be less than the nominal flag delay of 32ms in order to avoid nuisance
tripping of the /FAULT output since V
OUT
must be
“
fully on
”
(i.e., within
200mV of the voltage at the input) before the /FAULT signal delay elapses.
The slew-rate limiting capacitor requires a 16V rating or greater, 25V is
recommended. See
“
Applications Information: Output Slew-Rate Adjust-
ment
”
for further details.
6
ILIM
Current Limit (Input): A resistor (R
SET
) connected from this pin to ground
sets the current limit threshold as I
LIMIT
= CLF/R
SET
. CLF is the current limit
factor specified in the
“
Electrical Characteristics
”
table. For the MIC2044/45,
the continuous output current range is 1A to 6A.
5
UVLOIN
Undervoltage Lockout Adjust
(Input):
With this pin left open, the UVLO
threshold is internally set to 1.45V. When the switching voltage (V
IN
) is at or
below 1.5V, connecting an external resistive divider to this input will lower the
UVLO threshold. The total resistance of the divider must be less than 200k
.
To disable the UVLO, tie this pin to VIN. See
“
Applications Information
”
for
further detail.
7,11,13,16
VIN
Switch Supply (Input): Connected to the drain of the output MOSFET. The
range of input for the switch is 0.8V to 5.5V. These pins must be externally
connected together to achieve rated performance.
9,12,14
VOUT
Switch (Output): Connected to the source of the output MOSFET. These
pins must be externally connected together to achieve rated performance.
8
VBIAS
Bias Supply (Input): This input pin supplies power to operate the switch and
internal circuitry. The input range for VBIAS is 1.6V to 5.5V. When switched
voltage (V
IN
) is between 1.6V to 5.5V and the use of a single supply is
desired, connect VBIAS to VIN externally.
15
PGREF
Power-Good Threshold (Input): Analog reference used to specify the
PWRGD threshold. When the voltage at this pin exceeds its threshold, V
TH
,
PWRGD is asserted high. An external resistive divider network is used to
determine the output voltage level at which V
TH
is exceeded. See the
“
Functional Description
”
for further detail. When the PWRGD signal is not
utilized, this input should be tied to VOUT.
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