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參數(shù)資料
| 型號： | MIC2587R-2BM TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 4/22頁 |
| 文件大?。?/td> | 972K |
| 描述： | IC CTRLR HOT SWAP POS HV 8-SOIC |
| 標準包裝： | 2,500 |
| 類型： | 熱交換控制器 |
| 應(yīng)用： | 通用 |
| 內(nèi)部開關(guān)： | 無 |
| 電源電壓： | 10 V ~ 80 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | MIC2587R-2BMTR MIC2587R-2BMTR-ND |
icrel, Inc.
MIC2587/MIC2587R
anuary 24, 2013
4
Revision 2.0
Pin Description (Continued)
Pin Number
Pin Name
Pin Function
3
PWRGD
(MIC2587-1)
(MIC2587R-1)
Active-HIGH
/PWRGD
(MIC2587-2)
(MIC2587R-2)
Active-LOW
Power-is-Good (PWRGD or /PWRGD), Open-Drain Output: This pin remains de-asserted during
start up while the FB pin voltage is below the V
FBH
threshold. Once the voltage at the FB pin
rises above the V
FBH
threshold, the Power-is-Good output asserts with minimal delay
(typically d 5祍).
For the (1) options, the PWRGD output pin will be high-impedance when the FB pin voltage is
higher than V
FBH
and will pull down to GND when the FB pin voltage is less than V
FBL
.
For the (2) options, the /PWRGD output pin will be high-impedance when the FB pin voltage is
lower than V
FBL
and will pull down to GND when the FB pin voltage is higher than V
FBH
.
The Power-is-Good output pin is connected to an open-drain, N-channel transistor implemented
with high-voltage structures. These transistors are capable of operating with pull-up resistors to
supply voltages as high as 100V.
To use this signal as a logic control in low-voltage DC/DC conversion applications, an external
pull-up resistor between this pin and the logic supply voltage is recommended unless the DC/DC
module or other load is equipped with a internal pull-up impedance.
4
GND
Tie this pin directly to the systems analog GND plane.
5
TIMER
Current-Limit Response Timer: A capacitor connected from this pin to GND sets the time (t
FLT
)
for which the controller is allowed to remain in current limit before tripping the circuit breaker.
The overcurrent filter is designed to prevent nuisance tripping of the circuit breaker that can be
caused by transient current spikes or other undesired noise . Once the MIC2587 circuit breaker
trips, the output latches off. Under normal (steady-state) operation, the TIMER pin is held to
GND by an internal 3.5礎(chǔ) current source (I
TIMERDN
). When the voltage across the external sense
resistor exceeds the V
TRIP
threshold, an internal 65礎(chǔ) current source (I
TIMERUP
) is activated to
charge the capacitor connected to the TIMER pin. When the TIMER pin voltage reaches the
V
TIMERH
threshold, the circuit breaker is tripped pulling the GATE pin low, the I
TIMERUP
current
source is disabled, and the TIMER pin capacitor is discharged by the I
TIMERDN
current source.
When the voltage at the TIMER pin is less than 0.5V, the MIC2587 can be restarted by toggling
the ON pin LOW then HIGH.
For the MIC2587R, the GATE output attempts another start cycle to re-establish the output
voltage when the circuit breaker is tripped upon an overcurrent fault. The capacitor connected to
the TIMER pin sets the period of auto-retry with a fixed, nominal duty cycle of 5%.
6
GATE
Gate Drive Output: This pin is the output of an internal charge pump connected to the gate of an
external, N-channel power MOSFET. The charge pump has been designed to provide a
minimum gate drive (V
GATE
= V
GATE
V
CC
) of +7.5V over the input supplys full operating range.
When the ON pin voltage is higher than the V
ONH
threshold, a 16礎(chǔ) current source (I
GATEON
)
charges the GATE pin.
When in current limit, the output voltage at the GATE pin is adjusted so that the voltage across
the external sense resistor is held equal to V
TRIP
while the capacitor connected to the TIMER pin
charges. If the current limit condition goes away before the TIMER pin voltage rises above the
V
TIMERH
threshold, then steady-state operation resumes.
The GATE output pin is shut down whenever: (1) the input supply voltage is lower than the V
UVL
threshold, (2) the ON pin voltage is lower than the V
ONL
threshold, (3) the TIMER pin voltage is
higher than the V
TIMERH
threshold, or (4) the difference between the VCC and SENSE pins is
greater than V
TRIP
while the TIMER pin is grounded. For cases (3) and (4) overcurrent fault
conditions the GATE is immediately pulled to ground by I
GATEFLT
, an 80mA pull-down current
source.
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