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參數(shù)資料
| 型號： | MIC2590B-5BTQ TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 13/23頁 |
| 文件大?。?/td> | 230K |
| 描述： | IC PCI HOT PLUG CTLR DUAL 48TQFP |
| 標準包裝： | 2,000 |
| 類型： | 熱交換控制器 |
| 應(yīng)用： | PCI，PCI-X |
| 內(nèi)部開關(guān)： | 無 |
| 電源電壓： | 3.3V，5V，±12V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TQFP |
| 供應(yīng)商設(shè)備封裝： | 48-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | MIC2590B-5BTQTR MIC2590B-5BTQTR-ND |
Micrel, Inc.
MIC2590B
September 2008
13
M9999-091808
intended for use by systems that support the IPMI
standard, but may be used for any desired purpose.
Interrupt Generation
In the MIC2590B, the /INT pin can be asserted (driven
low) whenever a fault condition trips the circuit breaker.
The MIC2590B can thus operate in either polled mode or
interrupt mode. In the polled mode, the Interrupt Mask bit
in the Common Status Register should be set, to prevent
the /INT pin from being asserted. Upon a circuit breaker
fault event the appropriate status bit is also set in the
corresponding status registers. In order to clear the status
bit the system must write a logic 1 back to same bit in the
status register. Upon occurrence of the write the /INT pin
will be de-asserted (if interrupts were enabled), if no other
interrupts are pending. This method of echo reset allows
data to be retained in the status registers until such time
as the system software is ready to deal with that data, and
then to control the earliest time at which the next interrupt
might occur.
System Management Interface (SMI)
The MIC2590Bs System Management Interface uses the
Read_Byte and Write_Byte subset of the SMBus
protocols to communicate with its host via the System
Management Interface bus. Additionally, the /INT output
signals the controlling processor that one or more events
need attention, if an interrupt-driven architecture is used.
Note that theMIC2590B does not participate in the SMBus
Alert Response Address (ARA) portion of the SMBus
protocol.
The SMBus Read_Byte operation consists of sending the
devices slave address, followed by the target registers
internal address, and then clocking out the byte to be read
from the target register. Similarly, the Write_Byte
operation consists of sending the devices slave address,
followed by the target registers internal address, and then
clocking in the byte to be written to the target register. The
target register addresses for the MIC2590B are given in
Table 4.
MIC2590B SMBus Address Configuration
The MIC2590B responds to its own unique address which
is assigned using A2, A1 and A0. These represent the 3
LSBs of its 7-bit address, as shown in Table 3. These
address bits are assigned only during power up of the
V
STBY
supply input. These three bits allow up to eight
MIC2590B devices in a single system. These pins are
either grounded or left unconnected to specify a logical 0
or 1 respectively. A pin designated as a logical 1 may also
be pulled up to V
STBY
.
Inputs
MIC2590B Slave Addresses
A2 A1 A0
Binary
Hex
0
0
0
1000 000
b
80
h
0
0
1
1000 001
b
82
h
0
1
0
1000 010
b
84
h
0
1
1
1000 011
b
86
h
1
0
0
1000 100
b
88
h
1
0
1
1000 101
b
8A
h
1
1
0
1000 110
b
8C
h
1
1
1
1000 111
b
8E
h
Table 3. MIC2590B SMBus Addressing
AUXEN[x]
ON[x]
AUX OUT[x]
MAIN OUT[x]
FAULT DETECTED
ON AUX OUT[x]
FAULT DETECTED
ON MAIN OUT[x]
/FAULT OUTPUT[x]
/INT OUTPUT
(CLEARED BY SOFTWARE)
Figure 6. Hot Plug Interface Mode Operation
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