參數(shù)資料
型號: MIC5190
廠商: Micrel Semiconductor,Inc.
英文描述: ECONOLINE: RY & RX - Controllable Output- 1kVDC Isolation- No Heatsink Required- UL94V-0 Package Material- Toroidal Magnetics- No External Components- Fully Encapsulated- Efficiency to 70%
中文描述: 超高速,高電流有源濾波器/ LDO控制器
文件頁數(shù): 9/13頁
文件大?。?/td> 169K
代理商: MIC5190
April, 2
00
4
9
M9999-
0
428
0
4
M
IC
5
1
9
0
Micrel
T
he
V
IN
(min) to
V
OUT
ratio and current will determine the
maximum
R
DSON
required. For example, for a
1
.8
V
(
±
5%) to
1
.5
V
conversion at 5A of load current, dropout voltage can be
calculated as follows (using
V
IN
(min)):
(
R
V
V
I
R
1 71V 1
5
V
(
5A
R
m
DSON
IN
OUT
OUT
DSON
DSON
=
)
=
)
=
.
42
R
unning the
N
-
C
hannel in dropout will seriously affect tran-
sient response and
PSRR
(power supply ripple rejection). For
this reason, we want to select a M
OS
FE
T
that has lower than
42m
for our example application.
S
ize is another important consideration. Most importantly,
the design must be able to handle the amount of power being
dissipated.
T
he amount of power dissipated can be calculated as follows
(using
V
IN
(max)):
P
D
= (
V
IN
V
OUT
)
×
I
OUT
P
D
= (
1
.89
V
1
.5
V
)
×
5A
P
D
=
1
.95W
N
ow that we know the amount of power we will be dissipating,
we will need to know the maximum ambient air temperature.
For our case we’re going to assume a maximum of
6
5
°
C
ambient temperature.
D
ifferent M
OS
FE
T
s have different
maximum operating junction temperatures. Most M
OS
FE
T
s
are rated to
1
5
0
°
C
, while others are rated as high as
17
5
°
C
.
I
n this case, we’re going to limit our maximum junction
temperature to
1
25
°
C
.
T
he M
IC
5
1
9
0
has no internal thermal
protection for the M
OS
FE
T
so it is important that the design
provides margin for the maximum junction temperature.
O
ur
design will maintain better than
1
25
°
C
junction temperature
with
1
.95W of power dissipation at an ambient temperature of
6
5
°
C
.
O
ur thermal resistance calculates as follows:
S
o our package must have a thermal resistance less than
31
°
C
/W.
T
able
1
. shows a good approximation of power
dissipation and package recommendation.
Package
Power Dissipation
TSOP
-
6
<85
0
mW
TSSOP
-8
<95
0
mW
TSSOP
-8
<
1
W
P
ower
P
AK
1
2
1
2-8
<
1
.
1
W
SO
-8
<
1
.
1
25W
P
ower
P
AK
SO
-8
D
-
P
ack
<
1
.4W
TO
-22
0
/
TO
-2
63
(
D
2
P
ack)
>
1
.4W
Table 1. Power Dissipation and
Package Recommendation
I
n our example, our power dissipation is greater than
1
.4W, so we’ll choose a
TO
-2
63
(
D
2
P
ack)
N
-
C
hannel
M
OS
FE
T
.
θ
JA
is calculated as follows.
θ
JA
=
θ
J
C
+
θ
CS
+
θ
S
A
Where
θ
J
C
is the junction-to-case resistance,
θ
CS
is the
case-to-sink resistance and the
θ
S
A
is the sink-to-ambient
air resistance.
I
n the
D
2
package we’ve selected, the
θ
J
C
is 2
°
C
/W.
T
he
θ
CS
, assuming we are using the
PC
B as the heat sink, can
be approximated to
0
.2
°
C
/W.
T
his allows us to calculate
the minimum
θ
S
A
:
θ
S
A
=
θ
JA
θ
CS
θ
J
C
θ
S
A
=
31
°
C
/W –
0
.2
°
C
/W – 2
°
C
/W
θ
S
A
= 28.8
°
C
/W
R
eferring to Application Hint
17
,
D
esigning
PC
B Heat
S
inks the minimum amount of copper area for a
D
2
P
ack
at 28.8
°
C
/W is 2
7
5
0
mm
2
(or
0
.42
6
in
2
).
T
he solid line
denotes convection heating only (2 oz. copper) and the
dotted line shows thermal resistance with 25
0
LFM air-
flow.
T
he copper area can be significantly reduced by
increasing airflow or by adding external heat sinks.
Figure 8. PC Board Heat Sink
Another important characteristic is the amount of gate
capacitance. Large gate capacitance can reduce tran-
sient performance by reducing the ability of the M
IC
5
1
9
0
to slew the gate.
I
t is recommended that the M
OS
FE
T
used has an input capacitance <
10
nF (
C
ISS
).
θ
θ
θ
JA
J
J
D
°
JA
JA
T
max
(
T
ambient
)
(
P
1
25
C
6
5
C
1
.95W
C
W
°
31
=
)
=
°
=
/
Thermal Resistance vs. Area
PC Board Heat Sink
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