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參數(shù)資料
| 型號： | MIC70 |
| 廠商： | Micrel Semiconductor,Inc. |
| 英文描述： | 40000 SYSTEM GATE LOGIC CELL ARRAY - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | レP監(jiān)控電路 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 177K |
| 代理商： | MIC70 |
6
The output of the watchdog timer (WDO) will remain
high if WDI sees a valid transition within the watchdog
timeout period or if WDI is left floating. If VCC falls
below the reset threshold voltage then WDO goes low
immediately regardless of WDI. Thus, if WDI is left
floating, then WDO can be used as a low line indicator.
Microprocessor Reset
The RESET pin is asserted whenever VCC falls below
the reset threshold voltage or when MR goes low. The
reset pin remains asserted for a period of 200ms after
VCC has risen above the reset threshold voltage and
MR goes high. The reset function ensures the
microprocessor is properly reset and powers up into a
known condition after a power failure. RESET will
remain valid with VCCas low as 1.4V.
Power Fail Warning
An additional comparator which is independent of other
functions on the MIC705/706/707/708 is provided for
early warning of power failure. An external voltage
divider can be used to compare unregulated DC to an
internal 1.25V reference. The voltage divider ratio on
the input of the power fail comparator (PFI) can be
chosen so as to trip the power fail comparator a few
milliseconds before VCC falls below the maximum reset
threshold voltage. The output of the power fail
comparator (PFO) can be used to interrupt the
microprocessor when used in this mode and execute
shut-down procedures prior to power loss.
Watchdog Timer
The microprocessor can be monitored by connecting
the WDI pin (watchdog input) to a bus line or I/O line. If
a transition doesn’t occur on the WDI pin within the
watchdog timeout period, then WDO will go low. A
minimum pulse of 50ns or any transition low-to-high or
high-to-low on the WDI pin will reset the watchdog timer.
+
-
1.25V
R1
R2
Unregulated DC
PFO
PFI
Figure 3. Power Fail Comparator
Circuit Description
Figure 4. Reset Timing Diagram
VCC
MR
RESET
V
RT
t
MR
t
MD
t
RS
t
RS
WDO
MIC705/6/7/8
μ
P Supervisory Circuits
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MIC70_M | 40000 SYSTEM GATE 3.3 VOLT LOGIC CELL AR - NOT RECOMMENDED for NEW DESIGN |
| MIC70_N | レP Supervisory Circuits |
| MIC706 | μP Supervisory Circuit(μP監(jiān)控電路（帶看門狗定時器，電源故障警告和手動復位）) |
| MIC708 | μP Supervisory Circuit(μP監(jiān)控電路（帶電源故障警告和手動復位）) |
| MIC707 | μP Supervisory Circuit(μP監(jiān)控電路（帶電源故障警告和手動復位）) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MIC70__M | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:レP Supervisory Circuits |
| MIC70__N | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:レP Supervisory Circuits |
| MIC70_M | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:レP Supervisory Circuits |
| MIC70_N | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:レP Supervisory Circuits |
| MIC702 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interface serie pour afficheur LCD standard |
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