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參數(shù)資料
| 型號： | MIC7111BM5 |
| 廠商： | MICREL INC |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | 40000 SYSTEM GATE 3.3 VOLT LOGIC CELL AR - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | OP-AMP, 9000 uV OFFSET-MAX, 0.025 MHz BAND WIDTH, PDSO5 |
| 封裝： | SOT-23, 5 PIN |
| 文件頁數(shù)： | 6/8頁 |
| 文件大小： | 73K |
| 代理商： | MIC7111BM5 |
MIC7111
Application Information
Input Common-Mode Voltage
The MIC7111 tolerates input overdrive by at least 300mV
beyond either rail without producing phase inversion.
If the absolute maximum input voltage is exceeded, the input
current should be limited to
±
5mA maximum to prevent
reducing reliability. A 10k
series input resistor, used as a
current limiter, will protect the input structure from voltages as
large as 50V above the supply or below ground. See Figure
1.
Micrel
MIC7111
6
June 1998
V
IN
V
OUT
10k
R
IN
Figure 1. Input Current-Limit Protection
Output Voltage Swing
Sink and source output resistances of the MIC7111 are
equal. Maximum output voltage swing is determined by the
load and the approximate output resistance. The output
resistance is:
R
V
I
OUT
DROP
LOAD
=
V
DROP
is the voltage dropped within the amplifier output
stage. V
DROP
and I
LOAD
can be determined from the V
O
(output swing) portion of the appropriate Electrical Character-
istics table. I
LOAD
is equal to the typical output high voltage
minus V+/2 and divided by R
LOAD
. For example, using the
Electrical Characteristics DC (5V) table, the typical output
voltage drop using a 2k
load (connected to V+/2) is 0.015V,
which produces an I
LOAD
of:
2.5V
V
2k
then:
1.243mA
=
0 015
.
R
15mV
1.243mA
1
OUT
=
=
≈
12 1
2
.
Driving Capacitive Loads
Driving a capacitive load introduces phase-lag into the output
signal, and this in turn reduces op-amp system phase margin.
The application that is least forgiving of reduced phase
margin is a unity gain amplifier. The MIC7111 can typically
drive a 500pF capacitive load connected directly to the output
when configured as a unity-gain amplifier.
Using Large-Value Feedback Resistors
A large-value feedback resistor (> 500k
) can reduce the
phase margin of a system. This occurs when the feedback
resistor acts in conjunction with input capacitance to create
phase lag in the fedback signal. Input capacitance is usually
a combination of input circuit components and other parasitic
capacitance, such as amplifier input capacitance and stray
printed circuit board capacitance.
Figure 2 illustrates a method of compensating phase lag
caused by using a large-value feedback resistor. Feedback
capacitor C
FB
introduces sufficient phase lead to overcome
the phase lag caused by feedback resistor R
FB
and input
capacitance C
IN
. The value of C
FB
is determined by first
estimating C
IN
and then applying the following formula:
R
C
R
C
IN
IN
FB
FB
×
≤
×
V
IN
C
FB
R
FB
V
OUT
C
IN
R
IN
Figure 2. Cancelling Feedback Phase Lag
Since a significant percentage of C
IN
may be caused by board
layout, it is important to note that the correct value of C
FB
may
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