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參數(shù)資料
| 型號(hào)： | MJ-80C32E-30/883 |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 30 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | MQFP-44 |
| 文件頁(yè)數(shù)： | 18/20頁(yè) |
| 文件大?。?/td> | 239K |
| 代理商： | MJ-80C32E-30/883 |
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7
80C32E
Rev. K – 21-Aug-01
Idle mode
An instruction that sets PCON.0 causes that to be the last instruction executed before
going into the Idle mode. In the Idle mode, the internal clock signal is gated off to the
CPU, but not to the interrupt, Timer, and Serial Port functions. The CPU status is pre-
served in its entirely: the Stack Pointer, Program Counter, Program Status Word,
Accumulator, RAM and all other registers maintain their data during Idle. The port pins
hold the logical states they had at the time Idle was activated. ALE and PSEN hold at
logic high levels.
There are two ways to terminate the Idle. Activation of any enabled interrupt will cause
PCON.0 to be cleared by hardware, terminating the Idle mode. The interrupt will be ser-
viced, and following RETI the next instruction to be executed will be the one following
the instruction that put the device into idle.
The flag bits GF0 and GF1 can be used to give and indication if an interrupt occurred
during normal operation or during an Idle. For example, an instruction that activates Idle
can also set one or both flag bits. When Idle is terminated by an interrupt, the interrupt
service routine can examine the flag bits.
The over way of terminating the Idle mode is with a hardware reset. Since the clock
oscillator is still running, the hardware reset needs to be held active for only two
machine cycles (24 oscillator periods) to complete the reset.
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