參數(shù)資料
型號: MK1492-02RTRLF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘產(chǎn)生/分配
英文描述: 75 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28
封裝: 0.150 INCH, SSOP-28
文件頁數(shù): 7/7頁
文件大?。?/td> 70K
代理商: MK1492-02RTRLF
MK1492-02
Intel Mobile/SDRAM Clock Source
MDS1492-02E
7
Revision 2028
Printed 2/2/98
MicroClock Division of ICS1271 Parkmoor Ave.San JoseCA95126(408)295-9800tel(408)295-9818fax
PRELIMINARY INFORMATION
ICRO
CLOCK
While the information presented herein has been checked for both accuracy and reliability, MicroClock Incorporated assumes no responsibility for either its use or for the
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in
normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements
are not recommended without additional processing by MicroClock. MicroClock reserves the right to change any circuitry or specifications without notice. MicroClock does not
authorize or warrant any MicroClock product for use in life support devices or critical medical instruments.
b
D
E
H
e
Q
c
A
h x 45°
Package Outline and Package Dimensions
Ordering Information
Pentium is a trademark of Intel Corporation
28 pin SSOP
Inches
Millimeters
Symbol
Min
Max
Min
Max
A
0.061
0.068
1.55
1.73
b
0.008
0.012
0.203
0.305
c
0.007
0.010
0.190
0.254
D
0.385
0.400
9.780 10.160
E
0.150
0.160
3.810
4.064
H
0.230
0.245
5.840
6.223
e
.025 BSC
0.635 BSC
h
0.016
0.410
L
0.016
0.035
0.406
0.889
Q
0.004
0.01
0.127
0.254
Part/Order Number
Marking
Low EMI Feature
Package
Temperature
MK1492-02R
Yes
28 pin SSOP
0-70°C
MK1492-02RTR
MK1492-02R
Yes
Add Tape & Reel
-
I/O Structure
The MK1492 provides more functionality in a 28 pin package by using a
unique I/O technique. The device checks the status of all I/O pins during
power-up. This status (pulled high or low) then determines the frequency
selections and power down modes (see the tables on page 2). Within 10ms
after power up, the inputs change to outputs and the clocks start up. In the
diagrams to the right, the 33
resistors are the normal output
termination resistors. The 10k
resistor pulls low to generate a logic
zero. Internal pull-up resistors (approx. 100k
) are present on DS, SEL0,
FS, LE, CPUS#, PCISTP#, and CSSS. Internal resistors on PEN, SEL1,
and OE pull to a mid-level (M).
The CPUS# input should be connected as shown to implement the 0, M,
and 1 selections per the Power Down Control Table on page 2. Contact
MicroClock for suggested connections of PCISTP# if the PLL STOP
mode will be used.
to load
I/O
CPUS#
For select
= 0 (low)
10k
33
10k
CPU_STOP#
Don’t stuff for
“1” selection
10k
PWR_DOWN#
Signals from
North Bridge
L
相關PDF資料
PDF描述
MK1492-02RLF 75 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28
MK1492-04RTRLF 75 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28
MK1492-04RTR 75 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28
MK1492-04R 75 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28
MK1493-01G 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
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