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參數資料
| 型號： | MK1574-01BSITRLF |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 1574 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封裝： | 0.150 INCH, SOIC-16 |
| 文件頁數： | 8/10頁 |
| 文件大小： | 146K |
| 代理商： | MK1574-01BSITRLF |
FRAME RATE COMMUNICATIONS PLL
MDS 1574-01A/B B
7
Revision 051206
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l
www.icst.com
MK1574-01A/B
Loop Bandwidth and Loop Filter Component Selection
The series-connected capacitor and resistor between CAP1 and CAP2 (pins 4 and 6) determine the
dynamic characteristics of the phase-locked loop. The capacitor must have very low leakage, therefore a
high quality ceramic capacitor is recommended. DO NOT use any type of polarized or electrolytic
capacitor. The series connected capacitor and resistor between CAP1 and CAP2 (pins 4 and 6) determine
the dynamic characteristics of the phase-locked loop. The capacitor must have very low leakage, therefore
a high quality ceramic capacitor is recommended. DO NOT use any type of polarized or electrolytic
capacitor. Ceramic capacitors should have C0G or NP0 dielectric. Avoid high-K dielectrics like Z5U and
X7R; these and other ceramics which have piezoelectric properties allow mechanical vibration in the
system to increase the output jitter because the mechanical energy is converted directly to voltage noise
on the VCO input.
The values of the RC network determine the bandwidth of the PLL. The values of the loop filter
components are calculated using the constants K1 and K2 from the Loop Filter Constants table (page 7).
The loop bandwidth is set by the capacitor C and the constant K1 using the formula:
The loop damping is set by the resistor R, the capacitor C, and the constant K2 using the formula::
For example, to design the loop filter whewn generating 8.192 MHz from 8 kHz:
1. From the Output Clock Decoding table (page 2), the address is E. The Loop Filter Constants table (page
7) shows the constants K1 = 0.0516 and K2 = 6.2.
2. A good value for the loop bandwidth is 1/20 the input frequency; where 8 kHz/20 = 400 Hz. Using
equation 1,
Therefore,
3. A good value for the damping factor
ζ is 0.707. From equation 2,
BW (Hz) =
C
K1
Equation 1
R =
Equation 2;
ζ (zeta) is the damping factor
C
ζ * K2
C
K1
400 =
C
K1
C =
400
0.0516
(
) 2
= 16.6 nF (16 nF nearest standard value
R =
= 34.7 k
(36 k nearest standard value)
16E-9
0.707 * 6.2
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相關代理商/技術參數 |
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| MK1574-01BSTR | 功能描述:IC PLL FRAME RATE COMM 16-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數:- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| MK1574-01S | 功能描述:IC PLL FRAME RATE COMM 16-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數:1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| MK1574-01SI | 功能描述:IC PLL FRAME RATE COMM 16-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數:1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| MK1574-01SILF | 功能描述:時鐘發(fā)生器及支持產品 3.3V FRAME RATE COMMUNICATION PLL RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK1574-01SILFTR | 功能描述:時鐘發(fā)生器及支持產品 3.3V FRAME RATE COMMUNICATION PLL RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
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