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參數(shù)資料
| 型號： | MK1574-01SITR |
| 英文描述： | Frame Rate Communications PLL |
| 中文描述： | 幀速率通信鎖相環(huán) |
| 文件頁數(shù)： | 4/6頁 |
| 文件大小： | 83K |
| 代理商： | MK1574-01SITR |
MK1574
Frame Rate Communications PLL
MDS 1574-01 D
MicroClock Division of ICS 525 Race Street San Jose CA 95126(408)295-9800tel(408)295-9818fax
4
Revision 011999
Printed 11/15/00
ICRO
C
LOC K
The series-connected capacitor and resistor between CAP1 and CAP2 (pins 4 and 6) determine the dynamic
characteristics of the phase-locked loop. The capacitor must have very low leakage, therefore a high quality
ceramic capacitor is recommended. DO NOT use any type of polarized or electrolytic capacitor. The series
connected capacitor and resistor between CAP1 and CAP2 (pins 4 and 6) determine the dynamic
characteristics of the phase-locked loop. The capacitor must have very low leakage, therefore a high quality
ceramic capacitor is recommended. DO NOT use any type of polarized or electrolytic capacitor. Ceramic
capacitors should have C0G or NP0 dielectric. Avoid high-K dielectrics like Z5U and X7R; these and other
ceramics which have piezoelectric properties allow mechanical vibration in the system to increase the output
jitter because the mechanical energy is converted directly to voltage noise on the VCO input.
The values of the RC network determine the bandwidth of the PLL. The values of the loop filter components
are calculated using the constants K1 and K2 from the table on page 5. The loop bandwidth is set by the
capacitor C and the constant K1 using the formula
The loop damping is set by the resistor R, the capacitor C, and the constant K2 using the formula
Equation 2
;
ζ
(zeta) is the damping factor
For example, to design the loop filter when generating 8.192 MHz from 8 kHz:
1. From the table on page 2, the address is E. The table on page 5 shows constants K1=0.0516 and K2=6.2.
2. A good value for the loop bandwidth is 1/20 the input frequency; where 8 kHz/20 = 400 Hz. Using
Equation 1,
Therefore,
3. A good value for the damping factor
ζ
is 0.707. From Equation 2,
R =
C
ζ
K2
R =
0.707 6.2
16E-9
= 34.7 k
(36 k
nearest standard value)
Loop Bandwidth and Loop Filter Component Selection
Equation 1
BW (Hz) =
C
K1
400 =
C
0.0516
C =
400
0.0516
( )
2
= 16.6 nF (16 nF nearest standard value)
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| MK1574-01SLF | 功能描述:時鐘發(fā)生器及支持產品 3.3V FRAME RATE COMMUNICATION PLL RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK1574-01SLFTR | 功能描述:時鐘合成器/抖動清除器 3.3V FRAME RATE COMMUNICATION PLL RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MK1574-01STR | 功能描述:IC PLL FRAME RATE COMM 16-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| MK1575-01G | 功能描述:IC CLK RECOVERY PLL 16-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| MK1575-01GI | 功能描述:IC CLK RECOVERY PLL 16-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
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