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參數(shù)資料
| 型號： | MK1575-01GI |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封裝： | 4.40 MM, 0.65 MM PITCH, MO-153, TSSOP-16 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大小： | 217K |
| 代理商： | MK1575-01GI |
CLOCK RECOVERY PLL
MDS 1575-01 L
7
Revision 070605
In te gr ated Circuit Systems ● 525 Ra ce Street, San Jose, CA 9512 6 ● tel (4 08) 297-1 201 ● www.icst.com
MK1575-01
Input-to-Output Skew Induced by Loop
Filter Leakage
Leakage across the loop filter, due to PCB
contamination or poor quality loop filter capacitors, can
increase input-to-output clock skew error. Concern
regarding input-to-output skew error is usually limited to
“zero delay” configurations, where CLK1 or CLK2 is
directly connected to FBIN. In sever cases of loop filter
leakage, however, output clock jitter can also be
increased.
The capacitors CS and CP in the external loop filter
maintain the VCO frequency control voltage between
charge pump pulses, which by design coincide with
phase detector events. VCO frequency or phase
adjustments are made by these charge pump pulses,
pumping current into (or out of) the external loop filter
capacitors to adjust the VCO control voltage as
needed. Like the capacitors, the CHGP pin (pin 8) is a
high-impedance PLL node; the charge pump is a
current source, which is high impedance by definition,
and the VCO input is also high impedance.
During normal (locked) operation, in the event of
current leakage in the loop filter, the charge pump will
need to deliver equal and opposite charge in the form
of longer charge pump pulses. The increased length of
the charge pump pulse will be translated directly to
increased input-to-output clock skew. This can also
result in higher output jitter due to higher reference
clock feedthrough (where the reference clock is fREFIN),
depending on the loop filter attenuation characterisitcs.
The Input-to-Output skew parameters in the DC
Electrical Specifications assume minimal loop filter
leakage. Additional skew due to loop filter leakage may
be calculated as follows:
Avoiding PLL Lockup
In some applications, the MK1575-01 VCO can “l(fā)ock
up” at it’s maximum operating frequency. To avoid this
problem observe the following rules:
1) Do not open the clock feedback path with the
MK1575-01 enabled. If the MK1575-01 is enabled and
does not get a feedback clock into pin FBIN, the output
frequency will be forced to the maximum value by the
PLL.
If an external divider is in the feedback path and it has
a delay before becoming active, hold the OE pin high
until the divider is ready to work. This could occur, for
example, if the divider is implemented in a FPGA.
Holding OE high powers down the MK1575-01 and
dumps the charge off the loop filter.
2) If an external divider is used in the feedback path,
use a circuit that can operate well beyond the intended
output clock frequency.
Power Supply Considerations
As with any integrated clock device, the MK1575-01
has a special set of power supply requirements:
The feed from the system power supply must be
filtered for noise that can cause output clock jitter.
Power supply noise sources include the system
switching power supply or other system components.
The noise can interfere with device PLL components
such as the VCO or phase detector.
Each VDD pin must be decoupled individually to
prevent power supply noise generated by one device
circuit block from interfering with another circuit
block.
Clock noise from device VDD pins must not get onto
the PCB power plane or system EMI problems may
result.
This above set of requirements is served by the circuit
illustrated in the Optimum Power Supply Connection,
below. The main features of this circuit are as follows:
Only one connection is made to the PCB power
plane.
The capacitors and ferrite chip (or ferrite bead) on
the common device supply form a lowpass ‘pi’ filter
that remove noise from the power supply as well as
clock noise back toward the supply. The bulk
capacitor should be a tantalum type, 1
F minimum.
The other capacitors should be ceramic type.
The power supply traces to the individual VDD pins
should fan out at the common supply filter to reduce
interaction between the device circuit blocks.
Leakage Induced I/O Skew (sec)
I
Leakage
I
CP
F
REFIN
×
--------------------------------
=
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MK1575-01GILF | 功能描述:時鐘發(fā)生器及支持產品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK1575-01GILFTR | 功能描述:時鐘發(fā)生器及支持產品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK1575-01GITR | 功能描述:IC CLK RECOVERY PLL 16-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| MK1575-01GLF | 功能描述:時鐘發(fā)生器及支持產品 CLOCK RECOVERY PLL RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK1575-01GLFTR | 功能描述:時鐘發(fā)生器及支持產品 CLOCK RECOVERY PLL RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
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