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參數(shù)資料
| 型號： | MK1575-01GILFTR |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 10/14頁 |
| 文件大小： | 0K |
| 描述： | IC CLK RECOVERY PLL 16-TSSOP |
| 標準包裝： | 2,500 |
| 類型： | 時鐘和數(shù)據(jù)恢復（CDR），多路復用器 |
| PLL： | 是 |
| 主要目的： | 視頻 |
| 輸入： | 時鐘 |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 80MHz |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
MK1575-01
CLOCK RECOVERY PLL
CLOCK SYNTHESIZER
IDT CLOCK RECOVERY PLL
5
MK1575-01
REV P 051310
Setting PLL Loop Bandwidth and
Damping Factor
The frequency response of the MK1575-01 PLL may be
approximated by the following equation:
Normalized PLL Bandwidth
The associated damping factor is calculated as follows:
Damping factor,
Where:
KO =
VCO gain in Hz/Volt
(use 340 MHz/V)
Icp =
Charge pump current, 12.5
μA
N
=
Total feedback divide from VCO,
(Refer to N Value table, below)
CS =
External loop filter capacitor in Farads
RS =
Loop filter resistor in Ohms
The above bandwidth equation calculates the “normalized”
loop bandwidth which is approximately equal to the - 3dB
bandwidth. This approximate calculation does not take into
account the effects of damping factor or the third pole
imposed by CP. It does, however, provide a useful
approximation of filter performance.
To prevent jitter on the output clocks due to modulation of
the PLL by the input reference frequency, the following
general rule should be observed:
In general, the loop damping factor should be 0.7 or greater
to ensure output stability. For video applications, a low
damping factor (0.7 to 1.0) is generally desired for fast
genlocking. For telecom applications, a higher damping
factor is usually desirable. A higher damping factor will
create less passband gain peaking which will minimize the
gain of network clock wander amplitude. A higher damping
factor may also increase output clock jitter when there is
excess digital noise in the system application, due to the
reduced ability of the PLL to respond to, and therefore
compensate for, phase noise ingress.
Notes on setting the value of CP
As another general rule, the following relationship should be
maintained between components C1 and C2 in the external
loop filter:
Where:
CB = External bypass capacitor in Farads
Note that the MK1575-01 contains an internal 300 pF filter
cap which is connected in parallel with external device CB.
This helps to reduce output clock jitter. In some applications
external device CB will not be required.
CP establishes a second pole in the PLL loop filter. For
higher damping factors (>1), calculate the value of CP based
on a CS value that would be used for a damping factor of 1.
This will minimize baseband peaking and loop instability that
can lead to output jitter.
CP also helps to damp VCO input voltage modulation
caused by the charge pump correction pulses. A CP value
that is too low will result in increased output phase noise at
the phase detector frequency due to this. In extreme cases
where input jitter is high, charge pump current is high, and
CP is too small, the VCO input voltage can hit the supply or
ground rail resulting in non-linear loop response.
The best way to set the value of CP is to use the External
Loop Filter Solver located on the IDT web site.
R
S
K
O
I
CP
()
2
π N
-----------------------------------------------
=
ζ
R
S
2
--------
K
O
I
CP
C
S
N
------------------------------------------
=
PLL Bandwidth
f
Phase Detector
20
--------------------------------
≤
C
P
C
S
20
------
=
C
P
C
B
300 pF
+
=
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MK1575-01GITR | 功能描述:IC CLK RECOVERY PLL 16-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| MK1575-01GLF | 功能描述:時鐘發(fā)生器及支持產品 CLOCK RECOVERY PLL RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK1575-01GLFTR | 功能描述:時鐘發(fā)生器及支持產品 CLOCK RECOVERY PLL RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK1575-01GTR | 功能描述:IC CLK RECOVERY PLL 16-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| MK1581-01 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:LOW PHASE NOISE T1/E1 CLOCK GENERATOR |
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