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參數(shù)資料
| 型號(hào)： | MK1575-01GLFTR |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 1575 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封裝： | 4.40 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-16 |
| 文件頁數(shù)： | 7/14頁 |
| 文件大?。?/td> | 136K |
| 代理商： | MK1575-01GLFTR |
MK1575-01
CLOCK RECOVERY PLL
CLOCK SYNTHESIZER
IDT CLOCK RECOVERY PLL
2
MK1575-01
REV P 051310
Pin Assignment
16 pin 4.40 mil body, 0.65 mil pitch TSSOP
Pin Descriptions
12
1
11
2
10
REFIN
FBIN
3
9
FS0
4
VDDA
NC
5
VDDD
6
FCLK
7
FS1
8
GNDA
OE
CLK2
FS2
GNDD
CLK1
CHGP
CHPR
16
15
14
13
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
REFIN
Input
Reference clock input. Connect the input clock to this pin. Can be
Rising or Falling edge triggered as per Detailed Mode Selection Table,
page 3.
2FS0
Input
Frequency Selection Input bit 0, selects internal divider values as per
Detailed Mode Selection Table, page 3.
3
VDDA
Power
Power supply connection for internal VCO and other analog circuits.
4
VDDD
Power
Power supply connection for internal digital circuits and output buffers.
5FS1
Input
Frequency Selection Input bit 1, selects internal divider values as per
Detailed Mode Selection Table, page 3.
6
GNDA
Ground
Ground connection for internal VCO and other analog circuits.
7
GNDD
Ground
Ground connection for internal digital circuits and output buffers.
8
CHGP
—
Loop filter connection, active node.
9
CHPR
—
Loop filter connection, reference node. Do not connect to ground.
10
CLK1
Output
Output clock 1.
11
FS2
Input
Frequency Selection Input bit 2, selects internal divider values as per
Detailed Mode Selection Table, page 3.
12
CLK2
Output
Output clock 2.
13
OE
Input
Output Enable, tristates CLK1, CLK2, FCLK and powers down PLL
when high. Internal pull-up.
14
FCLK
Output
Feedback clock output, connect to FBIN for the pre-configured
frequency combinations listed in the tables on page 1.
15
NC
—
No internal connection, connect to ground.
16
FBIN
Input
Feedback clock input. Connect to CLK1, CLK2, FCLK, or the output of
an external feedback divider, depending on application. Refer to
document text for more information.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK1575-01GTR | 功能描述:IC CLK RECOVERY PLL 16-TSSOP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| MK1581-01 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:LOW PHASE NOISE T1/E1 CLOCK GENERATOR |
| MK1581-01GI | 功能描述:IC CLK GENERATOR T1/E1 16-TSSOP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MK1581-01GILF | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 LOW PHASE NOISE T1/E 1 CLOCK GENERATOR RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK1581-01GILFTR | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 LOW PHASE NOISE T1/E 1 CLOCK GENERATOR RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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