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參數(shù)資料
| 型號： | MK1709SLFTR |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 4/9頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK GENERATOR LOW EMI 8-SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 時鐘發(fā)生器 |
| PLL： | 是 |
| 輸入： | 時鐘 |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 167MHz |
| 除法器/乘法器： | 無/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
MK1709
LOW EMI CLOCK GENERATOR
SSCG
IDT LOW EMI CLOCK GENERATOR
4
MK1709
REV M 051310
External Components
The MK1709 requires a minimum number of external
components for proper operation.
Decoupling Capacitor
A decoupling capacitor of 0.01F must be connected
between VDD and GND on pins 2 and 3 for the MK1709S,
or pins 1 and 8 for the MK1709AG. Place the capacitor as
close to these pins as possible. For optimum device
performance, the decoupling capacitor should be mounted
on the component side of the PCB. Avoid the use of vias in
the decoupling circuit.
Series Termination Resistor
When the PCB trace between the clock output and the load
is over 1 inch, series termination should be used. To series
terminate a 50
trace (a commonly used trace impedance),
place a 33
resistor in series with the clock line, as close to
the clock output pin as possible. The nominal impedance of
the clock output is 20
.
Select Pin Operation
The S1, S0 select pins are 2-level, meaning they have three
separate states to make the selections shown in the table on
page 2.
PCB layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) The 0.01F decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between the decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via.
2) Place a 33
series termination resistor (if needed) close
to the clock output to minimize EMI.
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers. Other signal traces should be routed away from the
MK1709. This includes signal traces just underneath the
device, or on layers adjacent to the ground plane layer used
by the device.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK1709STR | 功能描述:IC CLK GENERATOR LOW EMI 8-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MK171 | 制造商:Velleman Inc 功能描述:Voice Changer Kit |
| MK171101 | 制造商:ICS 制造商全稱:ICS 功能描述:200 MHz Selectable Clock Source |
| MK1711-01 | 制造商:ICS 制造商全稱:ICS 功能描述:200 MHz Selectable Clock Source |
| MK1711-01S | 制造商:ICS 制造商全稱:ICS 功能描述:200 MHz Selectable Clock Source |
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