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參數(shù)資料
| 型號： | MK2042-01SI |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:19; Series:; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:14; Circular Contact Gender:Socket; Circular Shell Style:Cable Receptacle; Insert Arrangement:14-19 |
| 中文描述： | 通信時(shí)鐘監(jiān)視器 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 81K |
| 代理商： | MK2042-01SI |
MK2042-01
Communications Clock Monitor
MDS 2042-01
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126 (408)295-9800tel www.icst.com
3
Revision 102600
Printed 11/15/00
ICRO
C
LOC K
ADVANCE INFORMATION
Parameter
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage, VDD
Inputs and Clock Outputs
Ambient Operating Temperature
Soldering Temperature
Storage Temperature
DC CHARACTERISTICS (VDD = 3.3 V unless noted)
Operating Voltage, VDD
Input High Voltage, VIH (Note 2)
Input Low Voltage, VIL (Note 2)
Input High Voltage, VIH
Input Low Voltage, VIL
Output High Voltage, VOH, CMOS level
Output High Voltage, VOH
Output Low Voltage
Operating Supply Current, IDD
Short Circuit Current
Input Capacitance
AC CHARACTERISTICS (VDD = 3.3 V unless noted)
Input Frequency, External Mode
Input Clock Pulse Width
CLKOUT Settling Time
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle, High Time
Conditions
Minimum
Typical
Maximum
Units
Referenced to GND
7
V
V
°C
°C
°C
-0.5
-40
VDD+0.5
85
250
150
Max of 10 seconds
-65
3.14
5.25
V
V
V
V
V
V
V
V
INA, INB
INA, INB
IOH=-4 mA
IOH=-8 mA
IOL=8 mA
No Load, VDD=3.3 V
Each output
(VDD/2)+1
(VDD/2)-1
2
0.8
VDD-0.4
2.4
0.4
5
mA
mA
pF
±50
7
INA, INB, REFIN
0
4
100
MHz
ns
ms
ns
ns
%
After SELB change
0.8 to 2.0 V
2.0 to 0.8 V
At VDD/2
1
1.5
1.5
60
40
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure
to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. Switching occurs nominally at VDD/2.
3: The phase relationship between input and output clocks can change at power up or when switching between INA and INB.
Electrical Specifications
The MK2042-01 requires a minimum number of external components for proper operation. A decoupling
capacitor of 0.01μF must be connected between VDD and GND, pins 15 and 10. This capacitor should be
as close to the chip as possible. A series termination resistor of 33
may be used on CLKOUT with traces
longer than 1 inch (assuming 50
traces). In applications where the HIGH and LOW outputs are
connected to the MK2049-xx, 10 k
resistors should be used on each of those outputs.
EXTERNAL COMPONENT SELECTION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MK2042-01SITR | Communications Clock Monitor |
| MK2049-34SITR | 3.3 V Communications Clock PLL |
| MK2049-35SITR | 3.3 V Communications Clock PLL |
| MK2049-36SITR | 3.3 V Communications Clock PLL |
| MK2058-01SITR | Communications Clock Jitter Attenuator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK2042-01SITR | 制造商:ICS 制造商全稱:ICS 功能描述:Communications Clock Monitor |
| MK2049-01 | 制造商:ICS 制造商全稱:ICS 功能描述:Communications Clock PLL |
| MK2049-01S | 制造商:Integrated Device Technology Inc 功能描述:IC SM CLK GEN T1/E1/T3/E3 PLL 8KHZ P-SO- - Bulk |
| MK2049-01SI | 制造商:ICS 制造商全稱:ICS 功能描述:Communications Clock PLL |
| MK2049-01SITR | 制造商:ICS 制造商全稱:ICS 功能描述:Communications Clock PLL |
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